HIGH-SPEED 64K x 8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
x
x
PRELIMINARY
IDT709089S/L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
Commercial: 9/12/15ns (max.)
Low-power operation
IDT709089S
Active: 950mW (typ.)
Standby: 5mW (typ.)
IDT709089L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on Right Port via
the
FT/PIPER
pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
x
x
x
x
x
Full synchronous operation on both ports
4ns setup to clock and 1ns hold on all control, data,
and address inputs
Data input, address, and control registers
Fast 9ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
15ns cycle time, 66MHz operation in the Pipelined
output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (40°C to +85°C) is available
for selected speeds
Available in 84-pin Pin Grid Array (PGA) and 100-pin Thin
Quad Flatpack (TQFP) packages
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
I/O
Control
I/O
Control
A
15L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3242 drw 01
JUNE 1999
1
©1999 Integrated Device Technology, Inc.
DSC-3242/8
IDT709089S/L
High-Speed 64K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description:
The IDT709089 is a high-speed 64K x 8 bit synchronous pipelined
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers
on control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT709089 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by
CE
0
and CE
1,
permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDTs CMOS high-performance technology,
these devices typically operate on only 950mW of power.
Pin Configuration
(1,2,3)
Index
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
V
CC
NC
NC
NC
NC
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
V
CC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
4
72
1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
NC
NC
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
GND
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
NC
NC
IDT709089PF
PN100-1
(4)
100-PIN TQFP
TOP VIEW
(5)
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
GND
NC
NC
NC
NC
CE
0R
CE
1R
CNTRST
R
R/W
R
OE
R
FT/PIPE
R
GND
NC
3242 drw 02
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
5. This text does not indicate orientation of the actual part-marking.
GND
NC
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
NC
NC
NC
6.42
2
IDT709089S/L
High-Speed 64K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3)
(con't.)
63
61
60
58
55
54
51
48
46
45
11
66
A
7R
64
A
9R
A
10R
62
A
12R
59
A
15R
56
49
NC
50
NC
CE
0R
52
CNT
RST
R
47
OE
R
44
FT
/
PIPE
R
NC
42
NC
40
43
10
67
A
4R
65
A
6R
A
8R
A
11R
A
14R
57
CE
1R
53
R/W
R
GND
41
I/O
6R
39
09
69
A
3R
68
A
5R
A
13R
GND
NC
I/O
7R
38
I/O
5R
37
08
72
A
1R
71
A
2R
CNT
EN
R
A
0R
77
73
33
I/O
4R
35
I/O
3R
34
07
06
CLK
R
75
ADS
R
74
I/O
0R
IDT709089G
G84-3
(4)
84-PIN PGA
TOP VIEW
(5)
32
I/O
2R
31
I/O
1R
36
70
ADS
L
76
GND
78
GND
28
29
Vcc
30
Vcc
05
04
CLK
L
79
CNT
EN
L
A
2L
A
0L
GND
I/O1
L
26
I/O
0L
27
80
A
1L
81
83
I/O
3L
7
11
12
23
I/O
2L
25
03
82
A
3L
1
A
5L
2
5
8
A
13L
10
Vcc
14
NC
17
20
I/O
6L
22
I/O
4L
24
02
84
A
4L
3
A
7L
4
A
8L
6
A
11L
9
A
14L
15
NC
CE
0L
13
R/W
L
16
GND
18
I/O
7L
19
I/O
5L
21
01
A
6L
A
A
9L
B
A
10L
C
A
12L
D
A
15L
E
CE
1L
F
NC
G
CNT
RST
L
H
OE
L
J
Vcc
K
NC
.
L
3242 drw 03
INDEX
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.1in x 1.1in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
CE
0L
, CE
1L
R/
W
L
OE
L
A
0L
- A
15L
I/O
0L
- I/O
7L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
____
Right Port
CE
0R
, CE
1R
R/
W
R
OE
R
A
0R
- A
15R
I/O
0R
- I/O
7R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
FT
/PIPE
R
V
CC
GND
Names
Chip Enab le s
Re ad /Write Enab le
Outp ut Enab le
Ad d re ss
Data Inp ut/Outp ut
Clo ck
Ad d re ss Stro b e
Co unte r Enab le
Co unte r Re se t
Flo w-Thro ug h/Pip e line
Po we r
Gro und
3242 tb l 01
3
6.42
IDT709089S/L
High-Speed 64K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table I
Read/Write and Enable Control
(1,2,3)
OE
X
X
X
L
H
CLK
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
CE
1
X
L
H
H
H
R/
W
X
X
L
H
X
I/O
0-7
Hig h-Z
Hig h-Z
D
IN
D
OUT
Hig h-Z
Mode
De se le cte d
De se le cte d
Write
Re ad
Outp uts Disab le d
3242 tb l 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
Truth Table IIAddress Counter Control
(1,2)
Address
X
An
X
X
Previous
Address
X
X
An
An
CLK
↑
↑
↑
↑
ADS
H
L
(4)
H
H
CNTEN
H
H
H
L
(5)
CNTRST
L
H
H
H
I/O
(3)
D
I/O
(0)
D
I/O
(n)
D
I/O
(n)
D
I/O
(n+1)
Mode
Co unte r Re se t to Ad d re ss 0
Exte rnal Ad d re ss Utilize d
Exte rnal Ad d re ss Blo cke d —Co unte r Disab le d
Co unte r Enab le —Inte rnal Ad d re ss Ge ne ratio n
3242 tb l 03
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
is independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
6.42
4
IDT709089S/L
High-Speed 64K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Recommended Operating
Recommended DC Operating
(1,2)
Temperature and Supply Voltage
Conditions
Grade
Co mme rcial
Ind ustrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
3242 tb l 04
Symbol
V
CC
GND
V
IH
Parameter
Sup p ly Vo ltag e
Gro und
Inp ut Hig h Vo ltag e
Inp ut Lo w Vo ltag e
Min.
4.5
0
2.2
-0.5
(2)
Typ.
5.0
0
____
Max.
5.5
0
6.0
(1)
0.8
Unit
V
V
V
V
3242 tb l 05
NOTES:
1. This is the parameter T
A
.
2. Industrial temperature: for specific speeds, packages and powers contact
your sales office.
V
IL
____
NOTES:
1. V
TERM
must not exceed V
CC
+ 10%.
2. V
IL
> -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Te rminal Vo ltag e
with Re sp e ct
to GND
Te mp e rature
Und e r Bias
Sto rag e
Te mp e rature
DC Outp ut
Curre nt
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Capacitance
(1)
Symbol
C
IN
C
OUT
(3)
Parameter
Inp ut Cap acitance
(T
A
= +25°C, f = 1.0MH
z
) TQFP Only
Conditions
(2)
V
IN
= 3d V
V
OUT
= 3d V
Max.
9
10
Unit
pF
pF
3242 tb l 07
Outp ut Cap acitance
T
BIAS
T
STG
I
OUT
-55 to +125
-55 to +125
50
o
C
C
o
mA
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output
switch from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
3242 tb l 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
cc
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 10%.
5
6.42
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