Datasheet
μ
PD48576109
μ
PD48576118
576M-BIT Low Latency DRAM
Separate I/O
Description
The
μ
PD48576109 is a 67,108,864-word by 9 bit and the
μ
PD48576118 is a 33,554,432 word by 18 bit synchronous
double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
The
μ
PD48576109 and
μ
PD48576118 integrate unique synchronous peripheral circuitry and a burst counter. All input
registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These
products are suitable for application which require synchronous operation, high speed, low voltage, high density and
wide bit configuration.
R10DS0064EJ0300
Rev.3.00
Oct 01, 2012
Specification
•
Density: 576M bit
•
Organization
-
Separate I/O: 8M words x 9 bits x 8 banks
4M words x 18 bits x 8 banks
Features
•
SRAM-type interface
•
Double-data-rate architecture
•
PLL circuitry
•
Cycle time:
1.875 ns @ t
RC
= 15 ns
2.5 ns @ t
RC
= 15 ns
2.5 ns @ t
RC
= 20 ns
3.3 ns @ t
RC
= 20 ns
•
Operating frequency: 533 / 400 / 300 MHz
•
Interface: HSTL I/O
•
Package: 144-pin TAPE FBGA
-
Package size: 18.5 x 11
•
Non-multiplexed addresses
•
Multiplexing option is available.
•
Data mask for WRITE commands
•
Differential input clocks (CK and CK#)
•
Differential input data clocks (DK and DK#)
•
Data valid signal (QVLD)
•
Programmable burst length: 2 / 4 / 8 (x9 / x18)
•
User programmable impedance output (25
Ω
- 60
Ω)
•
JTAG boundary scan
-
Leaded and Lead free
•
Power supply
-
-
2.5 V V
EXT
1.8 V V
DD
-
1.5 V or 1.8 V V
DD
Q
•
Refresh command
-
-
Auto Refresh
16K cycle / 32 ms for each bank
-
128K cycle / 32 ms for total
•
Operating case temperature : Tc = 0 to 95°C
R10DS0064EJ0300 Rev.3.00
Oct 01, 2012
Page 1 of 51
μ
PD48576109,
μ
PD48576118
Ordering Information
Part number
Cycle
Clock
Random Organization Core Supply Core Supply Output Supply
Cycle
(word x bit)
Voltage
(V
EXT
)
Voltage
(V
DD
)
V
1.8 ± 0.1
Voltage
(V
DD
Q)
V
1.5 ± 0.1
or
1.8 ± 0.1
Package
Time Frequency
ns
MHz
533
400
400
300
533
400
400
300
533
400
400
300
533
400
400
300
ns
15
15
20
20
15
15
20
20
15
15
20
20
15
15
20
20
32 M x 18
64 M x 9
32 M x 18
64 M x 9
V
2.5 + 0.13
2.5 – 0.12
μ
PD48576109FF-E18-DW1-A
μ
PD48576109FF-E24-DW1-A
μ
PD48576109FF-E25-DW1-A
μ
PD48576109FF-E33-DW1-A
μ
PD48576118FF-E18-DW1-A
μ
PD48576118FF-E24-DW1-A
μ
PD48576118FF-E25-DW1-A
μ
PD48576118FF-E33-DW1-A
μ
PD48576109FF-E18-DW1
μ
PD48576109FF-E24-DW1
μ
PD48576109FF-E25-DW1
μ
PD48576109FF-E33-DW1
μ
PD48576118FF-E18-DW1
μ
PD48576118FF-E24-DW1
μ
PD48576118FF-E25-DW1
μ
PD48576118FF-E33-DW1
1.875
2.5
2.5
3.3
1.875
2.5
2.5
3.3
1.875
2.5
2.5
3.3
1.875
2.5
2.5
3.3
144-pin
TAPE FBGA
(18.5 x 11)
Lead-free
2.5 + 0.13
2.5 – 0.12
1.8 ± 0.1
1.5 ± 0.1
or
1.8 ± 0.1
144-pin
TAPE FBGA
(18.5 x 11)
Lead
R10DS0064EJ0300 Rev.3.00
Oct 01, 2012
Page 2 of 51
μ
PD48576109,
μ
PD48576118
Pin Arrangement
# indicates active LOW signal.
144-pin TAPE FBGA (18.5 x 11)
(Top View) [Separate I/O x9]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
(A22)
A21
A5
A8
BA2
NF
Note 2
Note 1
2
V
SS
DNU
DNU
DNU
DNU
DNU
A6
A9
NF
Note 2
Note 3
Note 3
3
V
EXT
DNU
DNU
DNU
DNU
DNU
A7
V
SS
V
DD
V
DD
V
SS
A17
DNU
DNU
DNU
DNU
DNU
V
EXT
Note 3
Note 3
Note 3
Note 3
4
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
5
6
7
8
9
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
10
V
EXT
Q0
Q1
QK0#
Q2
Q3
A2
V
SS
V
DD
V
DD
V
SS
A12
Q4
Q5
Q6
Q7
Q8
V
EXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D4
D5
D6
D7
D8
TDO
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
DK
REF#
WE#
A18
A15
V
SS
V
TT
V
DD
V
REF
DK#
CS#
A16
DNU
DNU
DNU
DNU
DNU
ZQ
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Notes 1.
Reserved for future use. This signal is internally connected and has parasitic characteristics of an address
input signal. This may optionally be connected to V
SS
, or left open.
2.
No function. This signal is internally connected and has parasitic characteristics of a clock input signal.
This may optionally be connected to V
SS
, or left open.
3.
Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may
optionally be connected to V
SS
.
CK, CK#
CS#
WE#
REF#
A0–A21
A22
BA0–BA2
D0–D8
Q0–Q8
DK, DK#
DM
QK0, QK0#
QVLD
: Input clock
: Chip select
: WRITE command
: Refresh command
: Address inputs
: Reserved for the future
: Bank address input
: Data input
: Data output
: Input data clock
: Input data Mask
: Output data clock
: Data Valid
ZQ
TMS
TDI
TCK
TDO
V
REF
V
EXT
V
DD
V
DD
Q
V
SS
V
SS
Q
V
TT
NF
DNU
: Output impedance matching
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: DQ Power Supply
: Ground
: DQ Ground
: Power Supply
: No function
: Do not use
R10DS0064EJ0300 Rev.3.00
Oct 01, 2012
Page 3 of 51
μ
PD48576109,
μ
PD48576118
# indicates active LOW signal.
144-pin TAPE FBGA (18.5 x 11)
(Top View) [Separate I/O x18]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
(A22)
(A21)
A5
A8
BA2
NF
Note 2
Note 1
Note 1
2
V
SS
D4
D5
D6
D7
D8
A6
A9
NF
Note 2
3
V
EXT
Q4
Q5
Q6
Q7
Q8
A7
V
SS
V
DD
V
DD
V
SS
A17
Q14
Q15
QK1#
Q16
Q17
V
EXT
4
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
5
6
7
8
9
V
SS
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
10
V
EXT
Q0
Q1
QK0#
Q2
Q3
A2
V
SS
V
DD
V
DD
V
SS
A12
Q9
Q10
Q11
Q12
Q13
V
EXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D9
D10
D11
D12
D13
TDO
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
DK
REF#
WE#
A18
A15
V
SS
V
TT
V
DD
V
REF
DK#
CS#
A16
D14
D15
QK1
D16
D17
ZQ
Notes 1.
Reserved for future use. This signal is internally connected and has parasitic characteristics of an address
input signal. This may optionally be connected to V
SS
, or left open.
2.
No function. This signal is internally connected and has parasitic characteristics of a clock input signal.
This may optionally be connected to V
SS
, or left open.
CK, CK#
CS#
WE#
REF#
A0–A20
A21–A22
BA0–BA2
D0–D17
Q0–Q17
DK, DK#
DM
QK0–QK1,QK0#–QK1#
QVLD
: Input clock
: Chip select
: WRITE command
: Refresh command
: Address inputs
: Reserved for the future
: Bank address input
: Data input
: Data output
: Input data clock
: Input data Mask
: Output data clock
: Data Valid
ZQ
TMS
TDI
TCK
TDO
V
REF
V
EXT
V
DD
V
DD
Q
V
SS
V
SS
Q
V
TT
NF
: Output impedance matching
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: DQ Power Supply
: Ground
: DQ Ground
: Power Supply
: No function
R10DS0064EJ0300 Rev.3.00
Oct 01, 2012
Page 4 of 51
μ
PD48576109,
μ
PD48576118
Pin Description
(1/2)
Symbol
CK, CK#
Type
Input
Clock inputs:
Description
CK and CK# are differential clock inputs. This input clock pair registers address and control inputs
on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS#
Input
Chip select
CS# enables the commands when CS# is LOW and disables them when CS# is HIGH. When the
command is disabled, new commands are ignored, but internal operations continue.
WE#, REF#
Input
WRITE command pin, Refresh command pin:
WE#, REF# are sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the
command to be executed.
A0–A21
Input
Address inputs:
A0–A21 define the row and column addresses for READ and WRITE operations. During a MODE
REGISTER SET, the address inputs define the register settings. They are sampled at the rising
edge of CK.
In the x18 configuration, A21 is reserved for address expansion. This expansion address can be
treated as address input, but it does not affect the operation of the device.
A22
Input
Reserved for future use:
These signals should be tied to V
SS
or leave open.
BA0–BA2
Input
Bank address inputs;
Select to which internal bank a command is being applied.
D0–Dxx
Input
Data input:
The D signals form the 18-bit input data bus. During WRITE commands, the data is referenced to
both edges of DK.
x 9 device uses D0 to D8.
x18 device uses D0 to D17.
Q0–Qxx
Output
Data output:
The Q signals form the 18-bit output data bus. During READ commands, the data is referenced to
both edges of QK.
x 9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
QKx, QKx#
Output
Output data clocks:
QKx and QKx# are opposite polarity, output data clocks. They are always free running and edge-
aligned with data output from the
μ
PD48576109/18. QKx# is ideally 180 degrees out of phase with
QKx.
For the x18 device, QK0 and QK0# are aligned with Q0–Q8. QK1 and QK1# are aligned with Q9–
Q17. For the x9 device, QK0 and QK0# are aligned with Q0–Q8.
DK, DK#
Input
Input data clock;
DK and DK# are the differential input data clocks. All input data is referenced to both edges of DK.
DK# is ideally 180 degrees out of phase with DK.
In both x9 and x18 configurations, all Ds are referenced to DK and DK#.
DM
Input
Input data mask;
The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled
HIGH along with the WRITE input data. DM is sampled on both edges of DK. The signal should be
V
SS
if not used.
QVLD
Output
Data valid;
The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#.
R10DS0064EJ0300 Rev.3.00
Oct 01, 2012
Page 5 of 51
医疗电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
