256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
DDR SDRAM
REGISTERED DIMM
Features
• 184-pin, dual, in-line memory module (DIMM)
• Fast data transfer rates: PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
• Registered Inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 256MB (32 Meg x 72); and 512MB (64 Meg x 72)
• V
DD
= V
DDQ
= +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence-Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
OPTIONS
MARKING
MT9VDDF3272 – 256MB
MT9VDDF6472 – 512MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 184-Pin DIMM (MO-206)
Low-Profile 1.125in. (28.58mm) 256MB
Low-Profile 1.125in. (28.58mm) 512MB
Very Low-Profile 0.72in. (18.29mm)
OPTIONS
MARKING
• Operating Temperature Range
Commercial (0°C
≤
T
A
≤
+70°C)
Industrial (-40°C
≤
T
A
≤
+85°C)
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)
1
• Memory Clock, Speed, CAS Latency
2
6ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
10ns (100 MHz), 200 MT/s, CL = 2
• PCB
Low-Profile 1.125in. (28.58mm)
Very Low-Profile 0.72in. (18.29mm)
NOTE:
G
Y
-335
-262
1
-26A
1
-265
-202
none
I
1
1. Contact Micron for product availability.
2. CL = CAS (READ) Latency; Registered mode will
add one clock cycle to CL.
Table 1:
Address Table
256MB
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
CONFIGURATION
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
MODULE
BANDWIDTH
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
MEMORY CLOCK/
DATA RATE
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
PART NUMBER
MT9VDDF3272G-335__
MT9VDDF3272Y-335__
MT9VDDF3272G-262__
MT9VDDF3272Y-262__
MT9VDDF3272G-26A__
MT9VDDF3272Y-26A__
MT9VDDF3272(I)G-265__
MT9VDDF3272(I)Y-265__
MT9VDDF3272(I)G-202__
MT9VDDF3272(I)Y-202__
MT9VDDF6472G-335__
MT9VDDF6472Y-335__
MT9VDDF6472G-262__
MT9VDDF6472Y-262__
MT9VDDF6472G-26A__
MT9VDDF6472Y-26A__
MT9VDDF6472(I)G-265__
MT9VDDF6472(I)Y-265__
MT9VDDF6472(I)G-202__
MT9VDDF6472(I)Y-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9VDDF3272G-265B1.
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DDQ
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
DNU
DNU
V
DDQ
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
DNU
SDA
SCL
Table 4:
Pin Assignment
(184-Pin DIMM Back)
PIN SYMBOL
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DQ47
NC
V
DDQ
DQ52
DQ53
NC
V
DD
DM6
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DM7
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
V
SS
DQ21
A11
DM2
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DDQ
DM3
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DDQ
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
DM8
A10
CB6
V
DDQ
CB7
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
DDQ
S0#
DNU
DM5
V
SS
DQ46
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
DDQ
DNU
DNU
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
PIN SYMBOL PIN SYMBOL PIN SYMBOL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
V
SS
DQ4
DQ5
V
DDQ
DM0
DQ6
DQ7
V
SS
NC
NC
NC
V
DDQ
DQ12
DQ13
DM1
V
DD
DQ14
DQ15
DNU
V
DDQ
NC
DQ20
A12
Figure 2: Pin Locations
Low-Profile – 256MB
Front View
U12
U1
U2
U3
U4
U5
U11
U13
U10
Back View
U6
U7
U8
U9
No Components This Side of Module
PIN 1
PIN 52
PIN 53
PIN 92
PIN 184
PIN 145
PIN 144
PIN 93
Front View
U6
U1
U2
U3
U4
U5
U8
U7
U9
U10
U11
Low-Profile – 512MB
Back View
U12
No Components This Side of Module
U13
PIN 1
PIN 52
PIN 53
PIN 92
PIN 184
PIN 145
PIN 144
PIN 93
Front View
U1
U2
U3
U4
U5
U6
U7
Very Low-Profile – all densities
Back View
U8
U9
U10
U11
U12
U13
PIN 1
PIN 52
PIN 53
PIN 92
PIN 184
PIN 145
PIN 144
PIN 93
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
Table 5:
Pin Descriptions
SYMBOL
Reset#
TYPE
Input
DESCRIPTION
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
10
63, 65, 154
137, 138
WE#, CAS#, RAS#
CK0, CK0#
21
CKE0
157
S0#
52, 59
BA0, BA1
27, 29, 32, 37, 41, 43, 48,
115, 118, 122, 125, 130,
141
A0–A12
97, 107, 119, 129, 140,
149, 159, 169, 177
5, 14, 25, 36, 47, 56, 67,
78, 86
44, 45, 49, 51, 134, 135,
142, 144
DM0–DM8
DQS0–DQS8
CB0–CB7
Asynchronously forces all registered ouputs LOW when RESET#
is LOW. This signal can be used during power-up to ensure CKE
is LOW and DQs are High-Z.
Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
DD
is applied and until
CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
Input Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Input Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM state does not affect READ
command.
Input/ Data Strobe: Output with READ data, input with WRITE data.
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Input/ Check Bits.
Output
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
Table 5:
Pin Descriptions
SYMBOL
DQ0–DQ63
TYPE
Input/ Data I/Os: Data bus.
Output
DESCRIPTION
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
2, 4, 6, 8, 12,13, 19, 20,
23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,
105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
92
181, 182, 183
91
SCL
SA0–SA2
SDA
1
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143,
156, 164, 172, 180
7, 38, 46, 70, 85, 108, 120,
148, 168
3, 11, 18, 26, 34, 42, 50,
58, 66, 74, 81, 89, 93, 100,
116, 124, 132, 139, 145,
152, 160, 176
184
16, 17, 75, 76, 90, 111,
158
9, 71, 82, 101, 102, 103,
113, 163, 167, 173
V
REF
V
DDQ
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-detect
portion of the module.
Supply SSTL_2 reference voltage.
Supply DQ Power Supply: +2.5V ±0.2V.
Input
V
DD
V
SS
Supply Power Supply: +2.5V ±0.2V.
Supply Ground.
V
DDSPD
DNU
NC
Supply Serial EEPROM positive power supply: .
—
Do Not Use: Thes pins are not connected on these modules, but
are assigned pins on other modules in this product family
—
No Connect: These pins should be left unconnected.
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
工业自动化与控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
