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Intel

®

StrongARM

®

SA-110

Microprocessor

Brief Datasheet

Product Features

The Intel

®

StrongARM

®

SA-110 Microprocessor (SA-110), the first

member of the StrongARM

®

family of high-performance, low-power

microprocessors, is optimized for meeting embedded consumer application

and portable application requirements. Offering power-saving features,

low cost, and high performance and price/performance, the SA-110 is a

solution for high-bandwidth network switching, intelligent office machines,

storage systems, and internet appliances, as well as digital cameras, bar-

code scanners, and other emerging consumer applications. In addition, to

delivering performance requirements in a low-power design, the SA-110

offers compatibility with existing ARM™ development tools and operating

systems.

s

High performance

—115 Dhrystone 2.1 MIPS @ 100 MHz

—185 Dhrystone 2.1 MIPS @ 160 MHz

—192 Dhrystone 2.1 MIPS @ 166 MHz

—230 Dhrystone 2.1 MIPS @ 200 MHz

—268 Dhrystone 2.1 MIPS @ 233 MHz

Low power

—<300 mW @1.65 V/100 MHz

—<450 mW @1.65 V/160 MHz

—<700 mW @2.0 V/166 MHz

—<900 mW @2.0 V/200 MHz

—<1000 mW @2.0 V/233 MHz

Internal phase-locked loop (PLL)

—3.68- or 3.56-MHz oscillator

Power-management features

—Idle (power-down) mode

—Sleep (power-down) mode

Big and little endian operating modes

s

144-pin thin quad flat pack (TQFP)

s

32-way set-associative caches

— 16 Kbyte instruction cache

— 16 Kbyte write-back data cache

s

32-entry MMUs

— Maps 4 Kbyte, 64 Kbyte, or 1 Mbyte

Write buffer

— 8-entry, 16 bytes each

Memory bus

— Asynchronous or synchronous

— 0-33 MHz @ 100 MHz

— 0-53 MHz @ 160 MHz

— 0-53 MHz @ 166 MHz

— 0-66 MHz @ 200 MHz

— 0-66 MHz @ 233 MHz

s

3.3-V I/O interface

Order Number:

278230-004

July 1999

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

ARM and the ARM Powered logo are trademarks and StrongARM is a registered trademark of ARM Limited.

2

SA-110 Brief Datasheet

SA-110 Microprocessor

Description

The SA-110 is a general-purpose, 32-bit RISC microprocessor with a 16 Kbyte instruction cache

(Icache); a 16 Kbyte write-back data cache (Dcache); a write buffer; and a memory-management

unit (MMU) combined in a single component. The five-stage pipeline distributes tasks evenly over

time to remove bottlenecks, ensuring high throughput for the core logic. The SA-110 on-chip

MMU supports a conventional two-level page-table structure, with a number of extensions. These

features result in a high instruction throughput and real-time response for a small and cost-effective

microprocessor.

Microarchitecture

The SA-110 CPU implements the ARM™ Version 4 architecture as defined in the

ARM

Architecture Reference Manual.

Figure 1

shows a block diagram of the SA-110.

Figure 1. Block Diagram of the SA-110

a<31:0>

abe

clf mas nrw lock

tck tdi tms ntrst tdo

nwait nmclk

clk

mccfg

mclk

sna

cccfg

Address Buffer

Test Access Port

Instruction

Clock

ape

Instruction

Memory-

Management

Unit

Data

Memory-

Management

Unit

Icache

PC

Core

Logic

Control

mse

nmreq

seq

config

npwrslp

abort

nirq

nfiq

nreset_out

Dcache

Address

dbe

Write Buffer

Load/Store Data

d<31:0>

nreset

LJ-04612.AI5

Bus Interface Logic

The bus interface logic, consisting of the control logic and the address register, controls the bus

interface and unplanned events such as interrupts, resets, and aborts. The bus interface logic can

also enable or disable wrapping of read transactions and merging of write transactions.

The bus interface can be configured to run synchronously or asynchronously to the core logic. In

synchronous mode, the bus interface clock speed is the core clock rate divided by a programmable

integer value from 2 to 9 (maximum of 66 MHz).

SA-110 Brief Datasheet

3

SA-110 Microprocessor

Write Buffer

The SA-110 has an 8-entry write buffer with each entry able to contain 1 byte to 16 bytes. The

write buffer can be enabled or disabled by software. The write buffer is further controlled by a bit

in the MMU page tables; so the MMU must be enabled before the write buffer can be used.

Software can cause the write buffer to be flushed.

Core Logic

The core logic fetches and executes instructions by using a five-stage pipeline. The five stages are:

fetch, decode, arithmetic logic unit (ALU), cache, and write-back. This pipeline arrangement,

using the on-chip ALU, distributes tasks evenly in time and, therefore, contributes to the high

performance of the core logic.

The ARM™ architecture supports 30 general-purpose registers, one program counter, and six

status registers. There are 16 general-purpose registers (including the PC register) and one or two

status registers visible at any one time. The processor operating mode determines which registers

are visible.

The core logic executes the ARM™ instruction set, which supports straight-forward assembly

language code programming. It does not depend upon sophisticated compilers to manage

complicated instruction interdependence. The instruction set has eight instruction classes:

•

Two instruction classes use the on-chip ALU, barrel shifter, and multiplier to perform high-

speed operations on the data in a bank of 16 logical (31 physical) 32-bit registers.

•

Three instruction classes control data transfer between memory and the registers. The classes

are optimized for flexible addressing, rapid context switching, and swapping data.

•

Two instruction classes control execution flow and execution privilege level.

•

One instruction class accesses the privileged state of the SA-110.

The core logic implements 32-bit virtual addresses and 32-bit physical addresses. A 12-bit

multiplier with early termination performs multiplication. The number of cycles needed to perform

a multiplication operation depends on the magnitude of the operands, as shown in

Table 1.

Core Logic Multiplication Functions

Multiplication Operation

(Signed or Unsigned)

32 x 32

32 x 32 + 32

32 x 32

32 x 32 + 64

Result Size

32 bits

64 bits

Operation Duration

2–4 cycles

3–5 cycles

Memory-Management Units

The SA-110 has two MMUs: instruction (IMMU) and data (DMMU). Separate translation look-

aside buffers (TLBs) are implemented for the instruction and data streams. The TLBs each have 32

entries that can each map a segment, a large page, or a small page. The TLB entry replacement

4

SA-110 Brief Datasheet

参数名称	属性值
零件包装代码	QFP
包装说明	LFQFP,
针数	144
Reach Compliance Code	unknow
地址总线宽度	32
位大小	32
边界扫描	YES
最大时钟频率	166 MHz
外部数据总线宽度	32
格式	FIXED POINT
集成缓存	NO
JESD-30 代码	S-PQFP-G144
长度	20 mm
低功率模式	YES
端子数量	144
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
认证状态	COMMERCIAL
座面最大高度	1.7 mm
速度	166 MHz
最大供电电压	1.815 V
最小供电电压	1.485 V
标称供电电压	1.65 V
表面贴装	YES
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
宽度	20 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC
Base Number Matches	1

	21281DB	21281CB
描述	32-BIT, 166 MHz, RISC PROCESSOR, PQFP144, TQFP-144	32-BIT, 200 MHz, RISC PROCESSOR, PQFP144, TQFP-144
零件包装代码	QFP	QFP
包装说明	LFQFP,	LFQFP,
针数	144	144
Reach Compliance Code	unknow	unknow
地址总线宽度	32	32
位大小	32	32
边界扫描	YES	YES
最大时钟频率	166 MHz	200 MHz
外部数据总线宽度	32	32
格式	FIXED POINT	FIXED POINT
集成缓存	NO	NO
JESD-30 代码	S-PQFP-G144	S-PQFP-G144
长度	20 mm	20 mm
低功率模式	YES	YES
端子数量	144	144
最高工作温度	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP
封装形状	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
认证状态	COMMERCIAL	COMMERCIAL
座面最大高度	1.7 mm	1.7 mm
速度	166 MHz	200 MHz
最大供电电压	1.815 V	1.815 V
最小供电电压	1.485 V	1.485 V
标称供电电压	1.65 V	1.65 V
表面贴装	YES	YES
温度等级	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm
端子位置	QUAD	QUAD
宽度	20 mm	20 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	1	1

21281DB

21281DB概述

21281DB规格参数

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