FEDR36V08G57C-002-02
Issue Date: Sep. 15, 2010
MR36V08G57C
262,144–Page
×
1,024 x 32–Bit
P2ROM (LVNROM)
PIN CONFIGURATION (TOP VIEW)
Vcc
Vss
NC
NC
I E#
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
D28
69
D20
68
D12
67
D4
66
D29
65
D21
64
D13
63
D5
62
D30
61
D22
60
D14
59
D6
58
D31
57
D23
56
D15
55
D7
54
OE#
53
NC
52
NC
51
Vcc
50
Vss
49
Vss
48
D0
47
D8
46
D16
45
D24
44
D1
43
D9
42
D17
41
D25
40
Vcc
39
D2
38
D10
37
D18
36
D26
FEATURES
Memory Configuration
•
262,144 x 1,024 x 32 bit
•
Multiplexed Command/Address/Data
Page Read Operation
•
Page Size
: 4,096 byte
•
Random access time : 1.0us (max) for block read
1.8us (max) for random read
•
Sequential Read
: 40ns (min)
•
Read Mode
Continuous Read : no wait for next page.
Page Read
: need wait time for next page
Power Supply Voltage
•
Vcc = 3.0 V to 3.6 V
PACKAGES
·70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC)
Vss
CE#
Vss
Vss
Vss
Vcc
Vss
NC
NC
NC
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor’s technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits over
the other non-volatile technologies, which include the
following;
·
Short lead time,
since the P2ROM is programmed at the final
stage of the production process, a large P2ROM inventory
"bank system" of un-programmed packaged products are
maintained to provide an aggressive lead-time and minimize
liability as a custom product.
·
No mask charge,
since P2ROMs do not utilize a custom mask
for storing customer code, no mask charges apply.
·
No additional programming charge,
unlike Flash and OTP
that require additional programming and handling costs, the
P2ROM already has the code loaded at the factory with
minimal effect on the production throughput. The cost is
included in the unit price.
·
Custom Marking is
available at no additional charge.
CLE
ALE
STE
NC
RST#
NC
RD/BY
Vss
D27
D19
D11
D3
70-pin SSOP
PDDC400565 1/14
FEDR36V08G57C-002-02
MR36V08G57C / P2ROM
BLOCK DIAGRAM
Row Decoder
CE#
I E#
OE#
CLE
ALE
STE
RST#
Memory Cell Matrix
262,144 x 1,024 x 32 bit
Control Logic
Column Decoder
Multiplexer & Sense Amp.
Page Register
Input/Output Buffer
RD/BY
D31
● ● ●
D0
PDDC400565 2/14
FEDR36V08G57C-002-02
MR36V08G57C / P2ROM
PIN DESCRIPTIONS
Pin name
I/O
Functions
Command/Address Input, Data Outputs
D31 to D0
I/O
The Data I/O are used to input command and address, and to output data during read
operation. The Data I/O float to high-z when the device is deselected or the outputs
are disabled.
Chip Enable
CE#
I
The CE# input activates the read operation. The CE# input shall stay “low” during the
read operation. The CE# input goes to “high”, the device returns to standby mode.
Input Enable
IE#
I
The IE# input controls the sequential data input during the read operation.
Commands and address are latched on the rising edge of the IE# pulse.
Output Enable
OE#
I
The OE# input controls the sequential data output during read operation. Data is valid
tOEA after the falling edge of OE# pulse, and the Data I/O goes to high-z tOEZ after
the rising edge of OE# pulse.
Command Latch Enable
CLE
I
The CLE input activates the latch of command inputs. When CLE is “high”, the inputs
are latched on the rising edge of IE# pulse.
Address Latch Enable
ALE
I
The ALE input activates the latch of address inputs. When ALE is “high”, the inputs
are latched on the rising edge of IE# pulse.
Status Output Enable
STE
I
The STE input activates the output of status. When STE is “high”, the status is valid
tOEA after the falling edge of OE# pulse, and the Data I/O goes to high-z at tOEZ
after the rising edge of OE# pulse.
Ready/Busy Output
RD/BY
O
The RD/BY output indicates the status of the device operation. When the RD/BY is
“low”, it indicates the read operation is not ready. When the read operation is ready,
the RD/BY goes “high”.
Reset
The RST# reset the whole circuits with low state. The RST# must be low at power on.
Power
Ground
No Connection
RST#
V
CC
V
SS
NC
I
-
-
-
PDDC400565 3/14
FEDR36V08G57C-002-02
MR36V08G57C / P2ROM
COMMAND INPUT
The lower 8 bits, D7 to D0, of the data inputs are valid, and the upper 24 bits, D31 to D8, of the data inputs are
“don’t care” in the command input.
Both Read and Stop command inputs are allowed in the ready state (RD/BY output = “high”) only. The Reset
command input is allowed in any states.
Command
1 Cycle
(CMD1)
st
2 Cycle
(CMD2)
nd
NOTE
This command is to read data sequentially from the start address.
Continuous
Read
00[H]
33[H]
This command continues until the next command is entered, the
maximum logic address is reached.
This command does NOT go to “busy” state at each page boundary.
This command is to read data sequentially from the start address.
Page
Read
00[H]
30[H]
This command continues until the next command is entered, the
maximum logic address is reached.
This command goes to “busy” state (RD/BY = “low”) at each page
boundary. The page size is 4K-Byte.
This command is to stop the read command.
This command is to reset (software reset) in any operations.
Stop
Reset
F0[H]
FF[H]
—
—
ADDRESS INPUT
The lower 8 bits, D7to D0, of the data inputs are valid, and the upper 24 bits, D31 to D8, of the data inputs are
“don’t care” in the address input.
The 1
st
cycle and 2
nd
cycle of the address input set up the column address. The column address can be set from
000[H] to 3FF[H]. The 3
rd
cycle to 5
th
cycle of the address input set up the row address. The row address can be set
from 00000[H] to 3FFFF[H].
Address Inputs
1 (CA0)
nd
2 (CA1)
3
rd
th
st
D[31:8]
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
D7
A7
L
A17
A25
L
D6
A6
L
A16
A24
L
D5
A5
L
A15
A23
L
D4
A4
L
A14
A22
L
D3
A3
L
A13
A21
L
D2
A2
L
A12
A20
L
D1
A1
A9
A11
A19
A27
D0
A0
A8
A10
A18
A26
(RA0)
4 (RA1)
th
5 (RA2)
PDDC400565 4/14
FEDR36V08G57C-002-02
MR36V08G57C / P2ROM
STATUS OUTPUT
The lower 8bits, D7 to D0, and another 8bits, D23 to D16, of the data outputs are used to output the status bits.
Other bits of the data outputs fixed “low” during status output.
Status Output Bit
D7 (D23)
D6 (D22)
D5 (D21)
D4 (D20)
Status value
0
Ready/Busy
0
CMD End
NOTE
—
This field indicates RD/BY output, Ready = H and Busy = L.
This status value is the same behavior with the RD/BY output signal.
—
This field indicates command operation status. “H” indicates the command
operation is completed, and “L” indicates the command operation is in
process.
This field indicates command input status. “H” indicates an error command
input such as invalid command code or invalid address. “L” indicates a
correct command input.
—
—
—
D3 (D19)
D2 (D18)
D1 (D17)
D0 (D16)
CMD Error
0
0
0
PDDC400565 5/14
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