1Gb: x4, x8, x16 DDR3L SDRAM
Description
1.35V DDR3L SDRAM
MT41K256M4 – 32 Meg x 4 x 8 banks
MT41K128M8 – 16 Meg x 8 x 8 banks
MT41K64M16 – 8 Meg x 16 x 8 banks
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 SDRAM (1.5V). Unless stated otherwise, DDR3L
SDRAM meets the functional and timing specifica-
tions listed in the equivalent density DDR3 SDRAM
data sheet located on www.micron.com.
• T
C
of 0°C to 95°C
– 64ms, 8192-cycle refresh at 0°C to 85°C
– 32ms at 85°C to 95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= +1.35V (1.283V to 1.45V)
Backward compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
Options
1
• Configuration
– 256 Meg x 4
– 128 Meg x 8
– 64 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball FBGA (8mm x 11.5mm) Rev. F, G
• FBGA package (Pb-free) – x16
– 96-ball FBGA (8mm x 14mm) Rev. G
• Timing – cycle time
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
• Revision
Note:
Marking
256M4
128M8
64M16
JP
JT
-125
-15E
:F, :G
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-125
1
-15E
1
-187E
Note:
Data Rate (MT/s)
1600
1333
1066
Target
t
RCD-
t
RP-CL (ns)
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.75
13.5
13.1
13.75
13.5
13.1
13.75
13.5
13.1
1. Backward compatible to 1066, CL = 7 (-187E).
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
256 Meg x 4
32 Meg x 4 x 8 banks
8K
16K A[13:0]
128 Meg x 8
16 Meg x 8 x 8 banks
8K
16K A[13:0]
64 Meg x 16
4 Meg x 16 x 8 banks
8K
8K A[12:0]
PDF: 09005aef833b7221
1Gb_1_35V_DDR3L.pdf - Rev. F 2/11 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 2: Addressing (Continued)
Parameter
Bank address
Column address
Page Size
256 Meg x 4
8 BA[2:0]
2K A[11, 9:0]
1KB
128 Meg x 8
8 BA[2:0]
1K A[9:0]
1KB
64 Meg x 16
8 BA[2:0]
1K A[9:0]
2KB
PDF: 09005aef833b7221
1Gb_1_35V_DDR3L.pdf - Rev. F 2/11 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)
1
A
V
SS
2
V
DD
V
SSQ
DQ2
3
NC
4
5
6
7
8
V
SS
V
SSQ
DQ3
9
V
DD
V
DDQ
V
SSQ
V
SSQ
NF, NF/TDQS#
B
V
SS
DQ0
DM, DM/TDQS
C
V
DDQ
DQS
DQ1
D
V
SSQ
NF, DQ6 DQS#
V
DD
V
SS
E
V
REFDQ
V
DDQ
NF, DQ4
V
SS
V
DD
CS#
RAS#
NF, DQ7 NF, DQ5 V
DDQ
CK
V
SS
V
DD
ZQ
NC
F
NC
G
ODT
CAS#
CK#
CKE
H
NC
WE#
A10/AP
NC
J
V
SS
BA0
BA2
NC
V
REFCA
BA1
V
SS
V
DD
V
SS
V
DD
V
SS
K
V
DD
A3
A0
A12/BC#
L
V
SS
A5
A2
A1
A4
M
V
DD
A7
A9
A11
A6
N
V
SS
RESET#
A13
NC
A8
Notes:
1. Ball descriptions listed in Table 3 (page 5) are listed as x4, x8 if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).
PDF: 09005aef833b7221
1Gb_1_35V_DDR3L.pdf - Rev. F 2/11 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Figure 2: 96-Ball FBGA – x16 Ball Assignments (Top View)
1
2
3
4
5
6
7
8
9
A
B
C
V
DDQ
V
SSQ
V
DDQ
DQ13
DQ15
DQ12
V
DDQ
DQ14
V
SS
V
SSQ
V
DDQ
V
DD
V
DDQ
V
SSQ
V
SSQ
V
DDQ
NC
V
DD
DQ11
V
SS
DQ9
UDQS#
UDQS
DQ10
D
V
SSQ
V
DDQ
V
SSQ
DQ2
UDM
DQ8
V
SSQ
V
SSQ
DQ3
E
V
SS
DQ0
LDM
F
V
DDQ
LDQS
DQ1
G
V
SSQ
DQ6
LDQS#
V
DD
DQ7
V
SS
DQ5
H
V
REFDQ
V
DDQ
V
SS
V
DD
CS#
DQ4
J
NC
RAS#
CK
V
SS
V
DD
ZQ
K
ODT
CAS#
CK#
CKE
L
NC
WE#
A10/AP
NC
M
V
SS
BA0
BA2
NC
V
REFCA
BA1
V
SS
V
DD
V
SS
V
DD
V
SS
N
V
DD
A3
A0
A12/BC#
P
V
SS
A5
A2
A1
A4
R
V
DD
A7
A9
A11
A6
T
V
SS
RESET#
NC
NC
A8
Notes:
1. Ball descriptions listed in Table 3 (page 5) are listed as x16.
2. A comma separates the configuration; a slash defines a selectable function.
PDF: 09005aef833b7221
1Gb_1_35V_DDR3L.pdf - Rev. F 2/11 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol
A[9:0], A10/AP,
A11, A12/BC#,
A13
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to V
REFCA
. A12/BC#: when enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-
mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,
LOW = BC4 burst chop).
Bank address inputs:
BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
V
REFCA
.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-
put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-
ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-
vides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-
ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-
cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V
REFCA
.
Chip select:
CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal rank selection on systems with multiple ranks. CS# is considered part of the command
code. CS# is referenced to V
REFCA
.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with the input data during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to V
REFDQ
. DM has an optional use as TDQS on the x8 device.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the
x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the
LOAD MODE command. ODT is referenced to V
REFCA
.
Command inputs:
RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to V
REFCA
.
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × V
DD
and DC LOW
≤
0.2 × V
DDQ
. RESET# assertion and de-assertion are asynchronous.
Data input/output:
Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-
enced to V
REFDQ
.
BA[2:0]
Input
CK, CK#
Input
CKE
Input
CS#
Input
DM
Input
ODT
Input
RAS#, CAS#, WE#
RESET#
Input
Input
DQ[3:0]
I/O
PDF: 09005aef833b7221
1Gb_1_35V_DDR3L.pdf - Rev. F 2/11 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
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