1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
Renesas Electronics Corporation
Product
Category
Title
MPU/MCU
Correction for Incorrect Description Notice
RL78/G10 Descriptions in the Hardware User’s Manual
Rev. 1.00 Changed
RENESAS TECHNICAL UPDATE
Document
No.
Information
Category
Date:
Feb. 6,
2014
TN-RL*-A023A/E
Rev.
1
.00
Technical Notification
Lot No.
Applicable
Product
RL78/G10
R5F10Yxxx
All lots
Reference
Document
RL78/G10 User’s Manual: Hardware
Rev.1.00
R01UH0384EJ0100 (Jun. 2013)
This document describes misstatements found in the RL78/G10 User’s Manual: Hardware Rev.1.00 (R01UH0384EJ0100).
Corrections
Applicable Item
Flash ROM: 4 KB of 10-pin products, and 16-pin
products
3. 1 Address Space
6. 3. 5 Timer channel enable status register 0
(TE0, TEH0 (8-bit mode))
6. 3. 8 Timer output enable register 0 (TOE0)
6. 4. 2 Basic rules of 8-bit timer operation function
(only channels 1 and 3)
Figure 10-13. Conversion Operation of A/D Converter
10. 9. 3 Conflicting operations
24. 3. 1 Pin characteristics
24. 6. 1 A/D converter characteristics
24. 6. 4 Data retention power supply voltage
characteristics
Applicable Page
Page 7
Pages 22 to 24
Page 121
Page 124
Page 132
Page 235
Page 242
Page 556
Page 567
Page 568
Contents
Specifications added
Incorrect descriptions revised
Incorrect descriptions revised
Incorrect descriptions revised
Specifications added
Incorrect descriptions revised
Descriptions added
Specifications extended
Specifications added
Descriptions added
Document Improvement
The above corrections will be made for the next revision of the User’s Manual: Hardware.
(c) 2014. Renesas Electronics Corporation. All rights reserved.
Page 1 of 13
RENESAS TECHNICAL UPDATE TN-RL*-A023A/E
Date:
Feb. 6,
2014
Corrections in the User’s Manual: Hardware
No.
1
2
3
4
5
6
7
8
9
10
Corrections and Applicable Items
Document No.
English
R01UH0384EJ0100
Flash ROM: 4 KB of 10-pin products, and 16-pin
Page 7
products
3. 1 Address Space
Pages 22 to 24
6. 3. 5 Timer channel enable status register 0
Page 121
(TE0, TEH0 (8-bit mode))
6. 3. 8 Timer output enable register 0 (TOE0)
6. 4. 2 Basic rules of 8-bit timer operation
function (only channels 1 and 3)
Figure 10-13. Conversion Operation of A/D
Converter
10. 9. 3 Conflicting operations
24. 3. 1 Pin characteristics
24. 6. 1 A/D converter characteristics
24. 6. 4 Data retention power supply voltage
characteristics
Page 124
Page 132
Page 235
Page 242
Page 556
Page 567
Page 568
Pages in this document
for corrections
Page 3
Pages 4 to 6
Page 7
Page 7
Page 7
Page 8
Page 9
Page 10
Pages 11 and 12
Page 13
Incorrect: Bold with underline;
Correct: Gray hatched
Revision History
RL78/G10 User’s Manual: Hardware Rev.1.00 Correction for Incorrect Description Notice
Document Number
TN-RL*-A023A/E
Date
Feb. 6,
2014
Description
First
edition issued
No.1 to 10 in corrections (This notice)
(c) 2014. Renesas Electronics Corporation. All rights reserved.
Page 2 of 13
RENESAS TECHNICAL UPDATE TN-RL*-A023A/E
Date: Feb. 6,
2014
1.
Flash ROM: 4 KB of 10-pin products, and 16-pin products (Page 7)
Flash ROM: 4 KB of 10-pin products and 16-pin products will be added to line-up in the group of RL78/G10.
The details of functions of 16-pin products will be made for the next revision of the User’s Manual:
Hardware.
This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H.
Item
R5F10Y14ASP
10-pin
R5F10Y16ASP
R5F10Y17ASP
R5F10Y44ASP
16-pin
R5F10Y46ASP
R5F10Y47ASP
Code flash memory
RAM
Main
system
clock
High-speed system
clock
1 KB
128 B
—
2 KB
256 B
4 KB
512 B
1 KB
128 B
2 KB
256 B
4 KB
512 B
X1, X2 (crystal/ceramic) oscillation, external
main system clock input (EXCLK):
1 to 20 MHz: V
DD
= 2.7 to 5.5 V
1 to 5 MHz: V
DD
= 2.0 to 5.5 V
Note 3
High-speed on-chip
oscillator clock
Low-speed on-chip oscillator clock
General-purpose register
Minimum instruction execution time
Instruction set
1.25 to 20 MHz (V
DD
= 2.7 to 5.5 V)
1.25 to 5 MHz (V
DD
= 2.0 to 5.5 V
Note 3
)
15 kHz (TYP)
8-bit register
8
0.05
s
(20 MHz operation)
Data transfer (8 bits)
Adder and subtractor/logical operation (8 bits)
Multiplication (8 bits
8 bits)
Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.
14
10 (N-ch open-drain output (V
DD
tolerance): 4)
4
4 channels
1 channel
4 channels (PWM outputs: 3
Note 1
I/O port
Total
CMOS I/O
CMOS input
8
6 (N-ch open-drain output (V
DD
tolerance): 2)
2
2 channels
1 channel
—
2 channels (PWM output: 1)
1
Timer
16-bit timer
Watchdog timer
12-bit interval timer
Timer output
)
Clock output/buzzer output
Comparator
8-/10-bit resolution A/D converter
Serial interface
I C bus
Vectored interrupt
sources
Key interrupt
Reset
Internal
External
2
2.44 kHz to 10 MHz: (Peripheral hardware clock: f
MAIN
= 20 MHz operation)
—
4 channels
2
2
1
7 channels
[10-pin products] CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
[16-pin products] CSI: 2 channels/simplified I C: 1 channel/UART: 1 channel
—
8
3
6
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by selectable power-on-reset
Note 2
Internal reset by illegal instruction execution
Internal reset by data retention lower limit voltage
Detection voltage
Rising edge (V
SPOR
): 2.25 V/2.68 V/3.02 V/4.45 V (max.)
Falling edge (V
SPDR
): 2.20 V/2.62 V/2.96 V/4.37 V (max.)
Note 3
1 channel
14
5
Selectable power-on-reset circuit
On-chip debug function
Power supply voltage
Operating ambient temperature
Provided
V
DD
= 2.0 to 5.5 V
T
A
= - 40 to + 85
C
Notes 1.
The number of outputs varies, depending on the setting of channels in use and the number of the master (see
6.9.4 Operation as multiple PWM output function).
2.
The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction
execution not issued by emulation with the on-chip debug emulator.
3.
Use this product within the voltage range from 2.25 to 5.5 V because the detection voltage (V
SPOR
) of the
selectable power-on-reset (SPOR) circuit should also be considered.
(c) 2014. Renesas Electronics Corporation. All rights reserved.
Page 3 of 13
RENESAS TECHNICAL UPDATE TN-RL*-A023A/E
Date:
Feb. 6,2014
2.
3. 1 Address Space (Pages 22 to 24)
Correct:
Incorrect:
(c) 2014. Renesas Electronics Corporation. All rights reserved.
Page 4 of 13
RENESAS TECHNICAL UPDATE TN-RL*-A023A/E
Incorrect:
Correct:
Date:
Feb. 6,2014
(c) 2014. Renesas Electronics Corporation. All rights reserved.
Page 5 of 13
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