Data Sheet
Rev.1.2
25.11.2010
2GB DDR2
– SDRAM registered DIMM
Features:
240 Pin RDIMM
SEP02G72D1BH2MT-25R
2GB PC2-6400 in FBGA Technology
RoHS compliant
240-pin 72-bit DDR2 registered Dual-In-Line Double Data
Rate Synchronous DRAM Module for server applications
Module organization: dual rank 256M x 72
V
DD
= 1.8V ±0.1V, V
DDQ
1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Supports ECC error detection and correction
JEDEC compatible DDR2 PLL/Register component with
parity bit support for address and control bus
Gold-contact pad
This module family is fully pin and functional compatible
to JEDEC. (see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 SDRAM component Micron
MT47H128M8CF-25 DIE-Rev. H
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 t
CK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
DLL to align DQ and DQS transitions with CK
Options:
Data Rate / Latency
DDR2 800MT/s CL6
DDR2 667MT/s CL5
Module Density
2048MB with 18 dies and 2 ranks
Standard Grade
(T
A
)
(T
C
)
0°C to 70°C
0°C to 85°C
Marking
-25
-30
Environmental Requirements:
Operating temperature (T
AMBIENT
)
Standard Grade
0°C to 70°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
mechanical dimensions
1
4.00
18.30
16.30
2.49
2.31
70.68
8.00
2.20
133.35
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 14
Data Sheet
Rev.1.2
25.11.2010
This Swissbit module is an industry standard 240-pin 8-byte DDR2 registered SDRAM Dual-In-line Memory
Module (RDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
256M x 72bit
DDR2 SDRAMs used
18 x 128M x 8bit (1024Mbit)
Row
Addr.
14
Device Bank
Select
BA0, BA1, BA2
Column
Refresh
Addr.
10
8k
Module
Bank Select
S0#, S1#
Module Dimensions
in mm
133.33 (long) x 18.3(high) x 4 [max] (thickness)
Timing Parameters
Part Number
SEP02G72D1BH2MT-25R
SEP02G72D1BH2MT-30R
Pin Name
A0 - A13
BA0, BA1
DQ0 – DQ63
CB0 – CB7
DM0-DM8
RAS#
CAS#
WE#
CKE0 – CKE1
CK0
CK0#
DQS0 – DQS17
DQS0# - DQS17#
CS0#, CS1#
Reset#
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Module Density
2048 MB
2048 MB
Transfer Rate
6.4 GB/s
5.3 GB/s
Clock Cycle/Data bit
rate
2.5ns/800MT/s
3.0ns/667MT/s
Latency
6-6-6
5-5-5
Address Inputs
Bank Address Inputs
Data Input / Output
Check Bits
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQs are High-Z.
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 14
Data Sheet
Rev.1.2
25.11.2010
P
AR
_IN
E
RR
_OUT
V
DD
/
V
DDQ
V
REF
V
SS
V
DDSPD
SCL
SDA
SA0 – SA1
ODT0, ODT1
NC
Parity bit for the address and control bus.
Parity error found on the address and control bus.
Supply Voltage (1.8V± 0.1V)
Input / Output Reference
Ground
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Front Side
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
VSS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
PIN #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front Side
A4
V
DDQ
A2
V
DD
V
SS
V
SS
V
DD
P
AR_
IN
V
DD
A10
BA0
V
DDQ
WE#
CAS#
V
DDQ
CS1#
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
PIN #
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back Side
V
SS
DQ4
DQ5
V
SS
DM0 (DQS9)
NC (DQS9#)
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1 (DQS10)
NC (DQS10#)
V
SS
CKE1
CKE1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2 (DQS11)
NC (DQS11)
V
SS
DQ22
DQ23
PIN #
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back Side
V
DDQ
A3
A1
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DDQ
RAS#
CS0#
V
DDQ
ODT0
A13
V
DD
V
SS
DQ36
DQ37
VSS
DM4 (DQS13)
NC (DQS13#)
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 14
Data Sheet
Rev.1.2
25.11.2010
PIN #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front Side
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
DD
CKE0
V
DD
BA2
E
RR
_OUT
V
DDQ
A11
A7
V
DD
A5
PIN #
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front Side
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC (TEST)
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
PIN #
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back Side
V
SS
DQ28
DQ29
V
SS
DM3 (DQS12)
NC (DQS12#)
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8 (DQS17)
NC (DQS17#)
V
SS
CB6
CB7
V
SS
V
DD
CKE1
V
DD
NC (A15)
NC (A14)
V
DD
A12
A9
V
DD
A8
A6
PIN #
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back Side
DM5 (DQS14)
NC (DQS14#)
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
NC (CK2)
NC (CK2#)
V
SS
DM6 (DQS15)
NC (DQS15#)
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7 (DQS16)
NC (DQS16#)
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 14
Data Sheet
Rev.1.2
25.11.2010
FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR2 ECC Registered DIMM,
2 RANKS AND 18 COMPONENTS
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 14
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