Data Sheet
Rev.1.0
23.06.2010
1GB DDR2
– SDRAM SO-DIMM
Features:
200 Pin SO-DIMM
SEN01G64E1CH2MT-30
1024MB PC2-5300 in FBGA Technique
RoHS compliant
200-pin 64-bit Small Outline, Dual-In-Line Double
Data Rate synchronous DRAM Module
Module organization: dual rank 128M x 64
Serial Presence Detect with EEPROM
DLL to align DQ and DQS transitions with CK
Adjustable data-output drive strength
Gold-contact pad
This module family is fully pin and functional
compatible to the JEDEC PC2-5300 spec. and
JEDEC- Standard MO 224C. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component base Micron
MT47H64M16 Die Rev. H
Options:
Frequency / Latency
DDR2 667 MHz CL5
Marking
-30
Module densities
1024MB with 8 dies and 2 ranks
Standard Grade
(t
A
)
(t
c
)
0° to 70°
C
C
0° to 85°
C
C
64Mx16 DDR2 SDRAM in FBGA-84 package
Environmental Requirements:
Operating temperature (ambient)
Standard Grade
0° to 70°
C
C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55° to 100°C
C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°
C
V
DD
= 1.8V ±0.1V, V
DDQ
1.8V ±0.1V
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
1.8V I/O ( SSTL_18 compatible)
Multiple internal device banks for concurrent
operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 t
CK
Programmable burst length: 4 or 8
Four bit prefetch architecture
On-die termination (ODT)
Figure:
mechanical dimensions
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 14
Data Sheet
Rev.1.0
23.06.2010
This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured oct-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
EEPROM using the standard I
2
C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
are utilized by the SO-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
128M x 64bit
DDR2 SDRAMs
used
8 x 64M x 16bit
(1Gbit)
Row Addr.
13
Device Bank
Col. Addr.
Select
BA0, BA1,
BA2
10
Refresh
8k
Module
Bank Select
S0#, S1#
Module Dimensions
in mm
67.60 (long) x 25.4(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SEN01G64E1CH2MT-30R
Module Density
1024 MB
Transfer Rate
5.3 GB/s
Memory clock/Data
bit rate
3.0ns/667MT/s
Latency
5300-555
Pin Name
A0-9, A11 – A12
A10/AP
BA0 –BA2
DQ0 – DQ63
DM0-DM7
RAS#
CAS#
WE#
CKE0 – CKE1
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 14
Data Sheet
Rev.1.0
23.06.2010
CK0 – CK1
CK0# – CK1#
DQS0 - DQS7
DQS0# - DQS7#
S0#, S1#
V
DD
V
REF
V
SS
V
DDSPD
SCL
SDA
SA0 – SA1
ODT0, ODT1
NC
Clock Inputs, positive line
Clock Inputs, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Supply Voltage (1.8V± 0.1V)
Input / Output Reference
Ground
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
PIN #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Front Side
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
PIN #
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Back Side
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
CK0#
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
DM2
PIN #
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
Front Side
A1
V
DD
A10/AP
BA0
WE#
V
DD
CAS#
S1#
V
DD
ODT1
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
DQ42
PIN #
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
Back Side
A0
V
DD
BA1
RAS#
S0#
V
DD
ODT0
NC/A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
DQ46
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 14
Data Sheet
Rev.1.0
23.06.2010
PIN #
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Front Side
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
NC/BA2
V
DD
A12
A9
A8
V
DD
A5
A3
PIN #
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Back Side
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
PIN #
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Front Side
DQ43
V
SS
DQ48
DQ49
V
SS
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DDSPD
PIN #
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back Side
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
CK1#
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 14
Data Sheet
Rev.1.0
23.06.2010
FUNCTIONAL BLOCK DIAGRAMM 1024MB DDR2 SDRAM SoDIMM,
2 RANKS AND 8 COMPONENTS
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 14
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