preliminary
Data Sheet
Rev.0.9
07.01.2013
4GB DDR2
– SDRAM registered SO-RDIMM
Features:
200 Pin SO-RDIMM
SEG04G72B1BC2MT-30R
4GByte in FBGA Technology
RoHS compliant
200-pin 72-bit Small Outline Registered Dual-In-Line
Double Data Rate Synchronous DRAM Module
Module organization: dual rank 512Mx72
V
DD
= 1.8V +0.1V, V
DDQ
= 1.8V +0.1V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Phase-lock loop (PLL) clock driver to reduce loading
Supports ECC error detection and correction
Gold-contact pad
This module family is fully pin and functional
compatible to the JEDEC PC2-5300 spec. and
JEDEC- Standard MO 224. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 SDRAM component Micron
Options:
Data Rate / Latency
DDR2 667 MT/s CL5
Module densities
4GB with 18 dies and 2 ranks
Standard Grade
(T
A
)
(T
C
)
0°C to 70°C
0°C to 85°C
Marking
-30
MT47H256M8EB-25E:C
256Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 t
CK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
DLL to align DQ and DQS transitions with CK
Environmental Requirements:
Operating temperature (T
C
)
Standard Grade
0°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Figure:
mechanical dimensions
1
the reference according MO224
Page 1
of 16
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
preliminary
Data Sheet
Rev.0.9
07.01.2013
This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Registered Dual-In-line
Memory Module (SO-RDIMM) which is organized as x72 high speed CMOS memory arrays. A Register
component and a PLL chip reduce loading on the clock and command/address bus. The module uses DDR2
SDRAM devices with eight internal banks. The module uses double data rate to achieve high-speed operation.
DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2
SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge
function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The
DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high
effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All inputs and all
full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
512M x 72bit
DDR2 SDRAMs used
18 x 256M x 8bit (2048Mbit)
Row
Addr.
15
Device Bank
Addr.
BA0, BA1, BA2
Column
Refresh
Addr.
10
8k
Module
Bank Select
S0#, S1#
Module Dimensions
in mm
67.6 (long) x 30.0(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SEG04G72B1BC2MT-30R
Module Density
2 GB
Transfer Rate
5.3 GB/s
Clock Cycle/Data bit
rate
3.0ns / 667MT/s
Latency
5-5-5
Pin Name
A0 - A14
BA0 – BA2
DQ0 – DQ63
CB0 – CB7
DM0-DM8
RAS#
CAS#
WE#
CKE0 / CKE1
CK0
CK0#
DQS0 - DQS8
DQS0# - DQS8#
S0# / S1#
Reset#
V
DD
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Address Inputs
Bank Address Inputs
Data Input / Output
Check Bits
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQs are High-Z.
Supply Voltage (1.8V± 0.1V)
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 16
preliminary
Data Sheet
Rev.0.9
07.01.2013
V
REF
V
SS
V
DDSPD
SCL
SDA
SA0 – SA1
ODT0 / ODT1
NC
Input / Output Reference
Ground
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
PIN #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
PIN #
Front Side
V
REF
DQ0
V
SS
DQ1
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
Front Side
PIN #
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
PIN #
Back Side
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
Reset#
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3
V
SS
DQ30
Back Side
PIN #
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
PIN #
Front Side
V
DD
A5
A3
A2
V
DD
A10 | AP
BA0
RAS#
V
DD
CAS#
S1#
V
DD
ODT1
NC (S3#)
DQ32
V
SS
DQ33
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
Front Side
PIN #
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
PIN #
Back Side
A6
A4
V
DD
A1
A0
BA1
V
DD
WE#
S0#
ODT0
A13
V
DD
CK0
CK0#
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5
V
SS
DQ46
DQ47
V
SS
DQ52
Back Side
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 16
preliminary
Data Sheet
Rev.0.9
07.01.2013
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CKE0
CKE1
NC (S2#)
V
DD
A12
A9
A7
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DQ31
V
SS
CB4
CB5
V
SS
DM8
V
SS
CB6
CB7
V
SS
CB2
CB3
V
SS
BA2
A14
A11
V
DD
A8
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
DQ58
V
SS
DQ59
V
DDSPD
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
DQ62
V
SS
DQ63
SDA
SCL
SA1
SA0
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 16
preliminary
Data Sheet
Rev.0.9
07.01.2013
FUNCTIONAL BLOCK DIAGRAMM 2GB DDR2 ECC Registered SoDIMM,
2 RANKS AND 18 COMPONENTS
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 16
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