Data Sheet
Rev.1.2
03.01.2013
2GB ECC DDR2
– SDRAM DIMM
Features:
240 Pin ECC UDIMM
SEU02G72D4BH2MT-XXR
2GByte in FBGA Technology
RoHS compliant
240-pin 72-bit Dual-In-Line Double Data Rate
synchronous DRAM Module with ECC support
V
DD
= 1.8V ±0.1V, V
DDQ
1.8V ±0.1V
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Gold-contact pad
This module is fully pin and functional compatible to
the JEDEC PC2-5300 spec. and JEDEC- Standard
MO-237. (see
www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component Micron
MT47H128M8CF-25 DIE-Rev.H
Options:
Data Rate / Latency
DDR2 667 MT/s CL5
DDR2 533 MT/s CL4
Marking
-30
-37
Module Density
2048MB with 18 dies and 2 ranks
Standard Grade
(T
A
)
(T
C
)
0°C to 70°C
0°C to 85°C
*) The refresh rate has to be doubled when 85°C<T
C
<95°C
Environmental Requirements:
Operating temperature
(AMBIENT)
Standard Grade
0°C to 70°C
Grade W
-40°C to 95°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 t
CK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
Figure:
mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
Page 1
of 16
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Data Sheet
Rev.1.2
03.01.2013
This Swissbit module is an industry standard 240-pin 8-byte DDR2 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
2
EEPROM using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
are utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
256M x 72bit
DDR2 SDRAMs used
18 x 128M x 8bit (1024Mbit)
Row
Addr.
14
Device Bank
Addr.
BA0, BA1, BA2
Column
Refresh
Addr.
10
8k
Module
Bank Select
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 28(high) x 4 [max] (thickness)
Timing Parameters
Part Number
SEU02G72D4BH2MT-30R
SEU02G72D4BH2MT-37R
Module Density
2048 MB
2048 MB
Transfer Rate
5.3 GB/s
4.2 GB/s
Clock Cycle/Data bit rate
3.0ns/667MT/s
3.75ns/533MT/s
Latency
5300-555
4200-444
Pin Name
A0-9, A11 – A13
A10/AP
BA0 – BA2
DQ0 – DQ63
CB0 – CB7
DM0-DM8
DQS0 – DQS8
DQS0# - DQS8#
RAS#
CAS#
WE#
CKE0 – CKE1
S0#, S1#
CK0 – CK1
CK0# – CK1#
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
ECC check bits
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Chip Select
Clock Inputs, positive line
Clock Inputs, negative line
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 16
Data Sheet
V
DD
V
DDQ
V
REF
V
SS
V
DDSPD
SCL
SDA
SA0 – SA2
ODT0, ODT1
NC
SDRAM core power supply (1.8V± 0.1V)
SDRAM I/O Driver power supply (1.8V± 0.1V)
Input / Output Reference
Ground
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Rev.1.2
03.01.2013
Pin Configuration
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Front Side
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC (RESET)
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
PIN #
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Back Side
V
SS
DQ4
DQ5
V
SS
DM0 (DQS9)
NC (DQS9#)
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1 (DQS10)
NC (DQS10#)
V
SS
CK1
CK1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2 (DQS11)
NC (DQS11#)
V
SS
DQ22
DQ23
V
SS
DQ28
PIN #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front Side
A4
V
DDQ
A2
V
DD
V
SS
V
SS
V
DD
NC (Par_In)
V
DD
A10/AP
BA0
V
DDQ
WE#
CAS#
V
DDQ
S1#
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5#
PIN #
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
Back Side
V
DDQ
A3
A1
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DDQ
RAS#
S0#
V
DDQ
ODT0
A13
V
DD
V
SS
DQ36
DQ37
V
SS
DM4 (DQS13)
NC (DQS13#)
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5 (DQS15)
NC (DQS15#)
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 16
Data Sheet
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front Side
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
DDQ
CKE0
V
DD
BA2
NC (Par_Out)
V
DDQ
A11
A7
V
DD
A5
PIN #
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back Side
DQ29
V
SS
DM3 (DQS12)
NC (DQS12#)
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8 (DQS17)
NC (DQS17#)
V
SS
CB6
CB7
V
SS
V
DDQ
CKE1
V
DD
NC (A15)
NC (A14)
V
DDQ
A12
A9
V
DD
A8
A6
PIN #
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front Side
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC (TEST)
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Rev.1.2
PIN #
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
03.01.2013
Back Side
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
NC (CK2)
NC (CK2#)
V
SS
DM6 (DQS15)
NC (DQS15#)
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7 (DQS16)
NC (DQS16#)
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 16
Data Sheet
FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR2 SDRAM ECC DIMM,
2 RANKS AND 18 COMPONENTS
CKE1
ODT1
S1
CKE0
ODT0
S0
CS ODT CKE
DQS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
CS ODT CKE
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Rev.1.2
03.01.2013
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D9
D4
D13
CS ODT CKE
DQS1
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
D1
D10
D5
D14
CS ODT CKE
DQS2
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
CS ODT CKE
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
CS ODT CKE
DQS3
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS7
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
D3
D12
D7
D16
CS ODT CKE
DQS8
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D17
V
DDSPD
V
REF
SPD
D0-D17
V
DD
/ V
DDQ
D0-D17
V
SS
D0-D17/SPD
SCL
SDA
BA0-BA2
A0-A13
RAS
CAS
WE
Serial PD
BA0-BA2: SDRAM D0-D17
A0-A13: SDRAM D0-D17
RAS: SDRAM D0-D17
CAS: SDRAM D0-D17
WE: SDRAM D0-D17
SA0
WP
SA1
SA2
SA2
SA0
SA1
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 16
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