FEDR45V256A-01
Issue Date: Nov. 12, 2013
MR45V256A
256k(32,768-Word
8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI
GENERAL DESCRIPTION
The MR45V256A is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. The MR45V256A is accessed using Serial
Peripheral Interface.Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required
to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as
those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the
power consumption during a write can be reduced significantly.
The MR45V256A can be used in various applications, because the device is guaranteed for the write/read
tolerance of 10
12
cycles per bit and the rewrite count can be extended significantly.
FEATURES
•
•
•
•
•
•
•
32,768-word
8-bit configuration (Serial Peripheral Interface : SPI)
A single 3.3 V
0.3 V power supply
Operating frequency:
15MHz
Read/write tolerance
10
12
cycles/bit
Data retention
10 years
Guaranteed operating temperature range
40
to 85C (Extended temperature version)
Package options:
8-pin plastic SOP (P-SOP8-200-1.27-T2K )
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FEDR45V256A-01
MR45V256A
PIN CONFIGURATION
8-pin plastic SOP
CS#
SO
WP#
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#
SCK
SI
Note:
Signal names that end with # indicate that the signals are negative-true logic.
MR45V256A
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MR45V256A
PIN DESCRIPTIONS
Pin Name
CS#
Description
Chip Select (input, negative logic)
Latches an address by low input, activates the FeRAM, and enables a read or write
operation.
Write Protect( input , negative logic )
WP#
Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should
be fixed low or high in write-operations.
HOLD( input , negative logic )
HOLD#
Hold pin is used when the serial-communication suspended without disable the chip
select. When HOLD# is low ,the serial-output is in High-Z status and
serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation.
Serial Clock
SCK
Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on
the rising edge and output occur on the falling edge.
Serial input
SI pins are serial input pins for Operation-code , addresses ,and data-inputs .
Serial output
SO pins are serial output pins.
Power supply
Apply the specified voltage to V
CC
. Connect V
SS
to ground.
SI
SO
V
CC
, V
SS
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FEDR45V256A-01
MR45V256A
SPI mode0（CPOL=0, CPHA=0）
CS#
SCK
SI
MSB
LSB
SPI mode3（CPOL=1, CPHA=1）
CS#
SCK
SI
MSB
LSB
Status Register
b7
SRWD
0
0
0
BP1
BP0
WEL
b0
WIP
Status Register Write Disable
Block Protect Bits
Write Enable Latch
Write In Progress (Always 0)
Name
WIP
WEL
BP0,BP1
SRWD
Function
Fixed to 0.
Write Enable Latch. This indicates internal WEL condition.
Block Protect :These bits can be changed protect area .
This is the software protect.
Status Register Write Disable
（
SRWD
）
: SRWD controls the effect of the
hardware WP# pin. This device will be in hardware-protect by combination of
SRWD and WP#.
Fixed to 0.
0
Status Register data are volatile.
Set Status Register data by WRSR(Write status register) command, after power on.
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MR45V256A
Operation-Code
Operation codes are listed in the table below.If the device receives invalid operation code,the device will be
diselected.
Instruction
Description
Instruction format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
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