FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
January 2000
FM93C56A
2K-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
The FM93C56A is 2048 bits of CMOS nonvolatile EEPROM (
Electrically Erasable Programmable Read Only Memory) with
MICROWIRE serial interface. FM93C56A can be configured for
either 128 x 16 bit or 256 x 8 bit array using an organization (ORG)
input pin. This device is fabricated using Fairchild Semiconductor's
floating gate CMOS process for high reliability, high endurance
and low power consumption. This device is available in 8-pin DIP,
SO and TSSOP packages.
The MICROWIRE serial interface offered by this EEPROM en-
ables simple interface to a wide variety of microcontrollers and
microprocessors. There are 7 instructions that operate the
FM93C56A: Read, Erase/Write Enable, Erase, Write, Erase/
Write Disable, Write All and Erase All.
Features
I
2.7V to 5.5V operation in all modes
I
Typical active current 200µA
10
µA
standby current typical
1
µA
standby current typical (L)
0.1
µA
standby current typical (LZ)
I
Self-timed programming cycle
I
Device status indication during programming mode
I
No erase required before write
I
Reliable CMOS floating gate technology
I
MICROWIRE compatible serial I/O
I
40 years data retention
I
Endurance: 1,000,000 data changes
I
Packages available: 8-Pin TSSOP, 8-pin SO, 8-pin DIP
I
Schmitt Trigger inputs and V
CC
lockout to prevent data
corruption
Block Diagram
CS
SK
Instruction
Register
Instruction
Decoder
Control Logic,
And Clock
Generators
VCC
DI
ORG
Address
Register
VPP
High Voltage
Generator
And
Program
Timer
Decoder
1 of 128
(or 256)
EEPROM Array
2048 Bits
(128x16) or (256x8)
Read/Write Amps
Data In/Out Register
16 (or 8) Bits
GND
DO
Data Out Buffer
DS800029-1
© 1999 Fairchild Semiconductor Corporation
FM93C56A Rev. A
1
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
–65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Operating Range
Ambient Operating Temperature
FM93C56AL/LZ
FM93C56ALE/LZE
FM93C56A LV/LZV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V to 5.5V
DC and AC Electrical Characteristics
V
CC
= 2.7V to 5.5V unless otherwise specified
Symbol
I
CCA
I
CCS
Parameter
Operating Current
Standby Current
L
LZ
Input Leakage
Input Leakage
ORG Pin
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Minimum CS
Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
Part Number
Conditions
CS = V
IH
, SK = 250KHz
CS = V
IL
Min.
Max.
1
10
1
Units
mA
µA
µA
µA
µA
µA
V
V
V
KHz
µs
µs
µs
µs
µs
ns
µs
ns
µs
I
IL
I
ILO
I
OL
V
IL
V
IH
V
OL
V
OH
f
SK
t
SKH
t
SKL
t
SKS
t
CS
t
CSS
t
DH
t
DIS
t
CSH
t
DIH
t
PD
t
SV
t
DF
t
WP
V
IN
= 0V to V
CC
(Note 2)
ORG tied to V
CC
ORG tied to V
SS
(Note 3)
V
IN
= 0V to V
CC
-0.1
0.8 V
CC
I
OL
= 10
µA
I
OH
= -10
µA
(Note 4)
0.9 V
CC
0
1
1
SK must be at V
IL
for
t
SKS
before CS goes high
(Note 5)
0.2
1
0.2
70
0.4
0
0.4
-1
-2.5
±1
1
2.5
±1
0.15 V
CC
V
CC
+1
0.1 V
CC
250
2
1
CS = V
IL
0.4
15
µs
µs
µs
ms
Capacitance
T
A
= 25°C, f = 1 MHz
Symbol
C
OUT
C
IN
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Test
Output Capacitance
Input Capacitance
Typ
Max
5
5
Units
pF
pF
Note 2:
Note 3:
Typical leakage values are in the 20 nA range.
The ORG pin may draw > 1
µA
when in the x8 mode ude to an internal pull-up transistor.
Note 4:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
f
SK
parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed.
Therefore, it is not allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 5:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in
the opcode diagrams in the following pages.)
AC Test Conditions
V
CC
Range
2.7V
≤
V
CC
≤
5.5V
(Extended Voltage Levels)
V
IL
/V
IH
Input Levels
.03V/1.8V
0.4V/2.4V
V
IL
/V
IH
Timing Level
1.0V
1.0V/2.0V
V
OL
/V
OH
Timing Level
0.8V/1.5V
0.4V/2.4V
I
OL
/I
OH
±10µA
2.1mA/-0.4mA
4.5V
≤
V
CC
≤
5.5V
(TTL Levels)
Output Load: 1 TTL Gate (C
L
= 100 pF)
4
FM93C56A Rev. A
www.fairchildsemi.com
FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
MICROWIRE I/O Pin Description
Chip Select (CS):
This pin enables and disables the MICROWIRE device and
performs 3 general functions:
1. When in the low state, the MICROWIRE device is disabled
and the output tri-stated (high impedance). If this pin is
brought high (rising edge active), all internal registers are
reset and the device is enabled, allowing MICROWIRE
communication via DI/DO pins. To restate, the CS pin must
be held high during all device communication and opcode
functions. If the CS pin is brought low, all functions will be
disabled and reset when CS is brought high again. The
exception to this is when a programming cycle is initiated
(see 2 and 3). Again, all activity on the CS, DI and DO pins
is ignored until CS is brought high.
2. After entering all required opcode and address data, bringing
CS low initiates the (asynchronous) programming cycle.
3. When programming is in progress, the Data-Out pin will
display the programming status as either BUSY (DO low) or
READY (DO high) when CS is brought high. (Again, the
output will be tri-stated when CS is low.) To restate, during
programming, the CS pin may be brought high and low any
number of times to view the programming status without
affect the programming operation. Once programming is
completed (Output in READY state), the output is 'cleared'
(returned to normal tri-state condition) by clocking in a Start
Bit. After the Start Bit is clocked in, the output will return to a
tri-stated condition. When clocked in, this Start Bit can be the
first bit in a command string, or CS can be brought low again
to reset all internal circuits.
Serial Clock (SK):
This pin is the clock input (rising edge active) for clocking in all
opcodes and data on the DI pin and clocking out all data on the DO
pin. However, this pin has no effect on the asynchronous program-
ming cycle (see the CS pin section) as the BUSY/READY status
is a function of the CS pin only.
Data-In (DI):
All serial communication into the device is performed using this
input pin (rising edge active). In order to avoid false Start Bits, or
related issues, it is advised to keep the DI pin in the low state
unless actually clocking in data bits (Start Bit, Opcode, Address or
incoming data bits to be programmed). Please note that the first
'1' clocked into the device (after CS is brought high) is seen as a
Start Bit and the beginning of a serial command string, so caution
must be observed when bringing CS high.
Data-Out (DO):
All serial communication
out of
the device, Read Data ( during
normal reads) as well as READY/BUSY status indication ( during
programming ) are performed using this output pin. Note that,
during READ operations, the EEPROM device starts to drive the
DO output pin "active" after the last address bit (A0) is clocked in.
Hence in applications where 3-wire configuration is required (
where DI and DO pins are tied together ) caution must be observed
for correct operation. Please refer AN-758 for further information.
Organization (ORG):
This pin controls the device architecture (8-bit data word vs. 16-bit
data word). If the ORG pin is brought to V
CC
, the device is
configured wiht a 16-bit data word and if the ORG pin is brought
to V
SS
(Ground), the device is configured with an 8-bit data word.
If the ORG pin is left floating, the device will default to a 16-bit data
word.
Instruction Set for the FM93C56A
ORG
Pin
Logic
0
1
Note:
Memory
Configuration
256 x 8
128 x 16
# of Address Bits
9 Bits
8 Bits
The leading (MSB) bit is a "don't care," but must be included in the address string.
5
FM93C56A Rev. A
www.fairchildsemi.com
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