Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 16,384 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UK08BGFM
DATA INTEGRITY
- 100,000 Program/Erase cycles (with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UK08BGFM-TP
: 48-pin TSOP DSP (12 x 20 x 2.3 mm)
-
HHY27UK08BGFM-TP (Lead Free)
- Program/Erase locked during Power transitions
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code.
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
: HY27UK08BGFM
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
Rev. 0.0 / Feb. 2007
Preliminary
HY27UK08BGFM Series
32Gbit (4Gx8bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UK08BGFM series is a 4Gx8bit capacity. The device is offered in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 16,384 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte block.
Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UK08BGFM extended reliability of 100K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27UK08BGFM is available in 48 - TSOP1 - DSP 12 x 20 mm package.
1.1 Product List
PART NUMBER
HY27UK08BGFM
ORIZATION
x8
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1
Rev. 0.0 / Feb. 2007
嵌入式系统
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