IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
FEATURES:
•
•
•
•
IDT54/74FCT543/A/C
•
•
•
•
•
•
•
•
•
IDT54FCT543 equivalent to FAST™ speed
IDT54/74FCT543A up to 25% faster than FAST
IDT74FCT543C up to 40% faster than FAST
Eqivalent to FAST output drive over full temperature and voltage
supply extremes
I
OL
= 64mA (commercial) and 48mA (military)
Separate controls for data flow in each direction
Back-to-back latches for storage
CMOS power levels (1mW typ. static)
Substantially lower input current levels than FAST (5µA max.)
µ
TTL input and output level compatible
CMOS output level compatible
MIlitary product compliant to MIL-STD-883, Class B
Available in the following packages:
– Commercial: SOIC
– Military: CERDIP, LCC
The FCT543 is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. These devices contain two sets of eight D-
type latches with separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB) input must be low
in order to enter data from A
0
–A
7
or to take data from B
0
–B
7
, as indicated
in the Function Table. With
CEAB
low, a low signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent; a subsequent
low-to-high transition of the
LEAB
signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs. With
CEAB
and
OEAB
both low, the 3-state B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B to A is similar,
but uses the
CEBA, LEBA
and
OEBA
inputs.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
DETAIL A
D
LE
A
0
3
Q
22
B
0
Q
D
LE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
4
5
6
7
8
9
10
21
B
1
20
B
2
19
DETAIL A x 7
B
3
18
B
4
17
B
5
16
B
6
15
B
7
OEBA
CEBA
LEBA
2
13
23
1
11
14
OEAB
CEAB
LEAB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
AUGUST 2003
DSC-4602/7
© 2003 Integrated Device Technology, Inc.
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEBA
NC
A
0
B
0
26
25
24
23
22
21
20
19
18
INDEX
OEBA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
GND
2
3
4
5
6
7
8
9
10
11
12
23
22
21
20
19
18
17
16
15
14
13
CEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
LEAB
OEAB
4
3
2
28
1
27
Vcc
LEBA
1
24
V
CC
LEBA
CEBA
A
1
A
2
A
3
NC
A
4
A
5
A
6
5
6
7
8
9
10
11
12
13
14
B
1
B
2
B
3
NC
B
4
B
5
B
6
15
16
17
CEAB
OEAB
LEAB
NC
A
7
CERDIP/ SOIC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Operating Temperature
Temperature under BIAS
Storage Temperature
Power Dissipation
DC Output Current
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
°C
°C
°C
W
mA
–0.5 to V
CC
–0.5 to V
CC
V
Commercial
–0.5 to +7
Military
–0.5 to +7
Unit
V
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
LOGIC SYMBOL
LEAB CEAB CEBA LEBA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
OEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OEAB
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
2
GND
LCC
TOP VIEW
B
7
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
B
0
–B
7
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
FUNCTION TABLE
(1, 2)
Inputs
LEAB
X
H
X
L
H
For A-to-B (Symmetric with B-to-A)
CEAB
H
X
X
L
L
OEAB
X
X
H
L
L
Latch
Status
A-to-B
Storing
Storing
X
Transparent
Storing
Output
Buffers
B
0
–B
7
High Z
X
High Z
Current A Inputs
Previous* A Inputs
NOTES:
1. * Before
LEAB
LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA
and
OEBA.
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V ±5%, Military: T
A
= -55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
OH
Off State (High Impedance)
Output Current
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Max.
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
V
CC
= Max.
Input LOW Current
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
O
= V
CC
V
O
= 2.7V
V
O
= 0.5V
V
O
= GND
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Min.
2
—
—
—
—
—
—
—
—
—
—
–60
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
10
10
(4)
–10
(4)
–10
–1.2
—
—
—
—
—
V
LC
V
LC
(4)
0.55
0.55
µA
µA
Unit
V
V
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µA
I
OH
= –300µA
V
CC
= Min
V
IN
= V
IH
or V
IL
I
OH
= –12mA MIL
I
OH
= –15mA COM'L
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µA
V
CC
= Min
I
OL
= 300µA
V
IN
= V
IH
or V
IL
I
OL
= 48mA MIL
I
OL
= 64mA COM'L
V
mA
V
V
OL
Output LOW Voltage
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not ttested.
3
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz (LEAB)
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Bit Toggling
at fi = 5MHz
V
CC
= Max.
Outputs Open
f
CP
= 10MHz (LEAB)
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
Eight Bits Toggling
at fi = 5MHz
V
IN
≥
V
HC
V
IN
≤
V
LC
Min.
—
—
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2
0.25
Unit
mA
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4
mA
—
2.2
6
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
7
12.8
(5)
—
9.2
21.8
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
∆I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54FCT543
Mil.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Parameter
Propagation Delay
Transparant Mode
Ax to Bx or Bx to Ax
Propagation Delay
LEBA
to Ax,
LEAB
to Bx
Output Enable Time
OEBA
or
OEAB
to Ax or Bx
CEBA
or
CEAB
to Ax or Bx
Output Disable Time
OEBA
or
OEAB
to Ax or Bx
CEBA
or
CEAB
to Ax or Bx
Set-up Time, HIGH or LOW
Ax or Bx to
LEBA
or
LEAB
Hold Time, HIGH or LOW
Ax or Bx to
LEBA
or
LEAB
LEBA
or
LEAB
Pulse Width LOW
5
—
5
—
5
—
5
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
54/74FCT543A
Com'l.
Mil.
2.5
7.5
Min
.
(2)
Max.
2.5
6.5
74FCT543C
Com'l.
Unit
ns
2.5
5.3
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min
.
(2)
2.5
Max.
10
Min
.
(2)
Max. Min
.
(2)
Max.
2.5
2
14
14
2.5
2
8
9
2.5
2
9
10
2.5
2
7
8
ns
ns
2
13
2
7.5
2
8.5
2
6.5
ns
3
2
—
—
2
2
—
—
2
2
—
—
2
2
—
—
ns
ns
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
