IRF830S, SiHF830S, IRF830L, SiHF830L
www.vishay.com
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
V
DS
(V)
R
DS(on)
()
Q
g
max. (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
38
5.0
22
Single
D
FEATURES
500
1.5
•
•
•
•
•
•
•
•
Surface mount
Available in tape and reel
Dynamic dV/dt rating
Available
Repetitive avalanche rated
Fast switching
Available
Ease of paralleling
Simple drive requirements
Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
I
2
PAK
(TO-262)
D
2
PAK (TO-263)
G
G
D
S
G
D
S
S
N-Channel MOSFET
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D
2
PAK (TO-263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D
2
PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D
2
PAK (TO-263)
SiHF830S-GE3
IRF830SPbF
D
2
PAK (TO-263)
SiHF830STRL-GE3
a
IRF830STRLPbF
a
I
2
PAK (TO-262)
SiHF830L-GE3
IRF830LPbF
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
a
Linear Derating Factor
Linear Derating Factor (PCB mount)
e
Single Pulse Avalanche Energy
b
Avalanche Current
a
Repetitive Avalanche Energy
a
Maximum Power Dissipation
Maximum Power Dissipation (PCB mount)
e
Peak Diode Recovery dV/dt
c
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature)
d
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
LIMIT
500
± 20
4.5
2.9
18
0.59
0.025
280
4.5
7.4
74
3.1
3.5
-55 to +150
300
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
E
AS
I
AR
E
AR
T
C
= 25 °C
T
A
= 25 °C
P
D
dV/dt
T
J
, T
stg
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 24 mH, R
g
= 25
,
I
AS
= 4.5 A (see fig. 12).
c. I
SD
4.5 A, dI/dt
75 A/μs, V
DD
V
DS
, T
J
150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
S16-0754-Rev. E, 02-May-16
Document Number: 91064
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF830S, SiHF830S, IRF830L, SiHF830L
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
Maximum Junction-to-Ambient
(PCB mount)
a
Maximum Junction-to-Case (Drain)
SYMBOL
R
thJA
R
thJA
R
thJC
TYP.
-
-
-
MAX.
62
40
1.7
°C/W
UNIT
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
Gate Input Resistance
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
Current
a
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
R
g
TEST CONDITIONS
V
GS
= 0, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 20 V
V
DS
= 500 V, V
GS
= 0 V
V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 2.7 A
b
A
b
V
DS
= 50 V, I
D
= 2.7
MIN.
500
-
2.0
-
-
-
-
2.5
-
-
-
-
-
-
-
-
-
-
TYP.
-
0.61
-
-
-
-
-
-
610
160
68
-
-
-
8.2
16
42
16
4.5
7.5
-
MAX.
-
-
4.0
± 100
25
250
1.5
-
-
-
-
38
5.0
22
-
-
-
-
-
UNIT
V
V/°C
V
nA
μA
S
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
I
D
= 3.1 A, V
DS
= 400 V,
see fig. 6 and 13
b
pF
V
GS
= 10 V
nC
V
DD
= 250 V, I
D
= 3.1 A,
R
g
= 12
,
R
D
= 79
,
see fig. 10
b
Between lead,
6 mm (0.25") from
package and center of
die contact
D
ns
-
G
nH
-
S
-
2.7
f = 1 MHz, open drain
0.5
-
-
-
-
-
-
-
-
320
1.0
4.5
A
18
1.6
640
2.0
V
ns
μC
G
S
T
J
= 25 °C, I
S
= 4.5 A, V
GS
= 0 V
b
T
J
= 25 °C, I
F
= 3.1 A, dI/dt = 100 A/μs
b
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width
300 μs; duty cycle
2 %.
S16-0754-Rev. E, 02-May-16
Document Number: 91064
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF830S, SiHF830S, IRF830L, SiHF830L
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
Vishay Siliconix
10
1
Top
I
D
, Drain Current (A)
10
0
V
GS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
4.5 V
I
D
= 3.1 A
V
GS
= 10 V
10
-1
10
0
91064_01
20 µs Pulse Width
T
C
=
25 °C
10
1
20 40 60 80 100 120 140 160
V
DS
, Drain-to-Source Voltage (V)
91064_04
T
J,
Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics, T
C
= 25 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
10
1
I
D
, Drain Current (A)
Capacitance (pF)
10
0
V
GS
Top
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
1500
1250
1000
750
500
250
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
4.5 V
C
iss
C
oss
10
-1
91064_02
20 µs Pulse Width
T
C
=
150 °C
10
0
10
1
91064_05
0
10
0
C
rss
10
1
V
DS,
Drain-to-Source Voltage (V)
V
DS,
Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, T
C
= 150 °C
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
150
°
C
V
GS
, Gate-to-Source Voltage (V)
10
1
I
D
= 3.1 A
V
DS
= 400 V
V
DS
= 250 V
I
D
, Drain Current (A)
16
25
°
C
10
0
12
V
DS
= 100 V
8
4
For test circuit
see figure 13
10
-1
4
91064_03
20 µs Pulse Width
V
DS
=
50 V
5
6
7
8
9
10
0
0
91064_06
8
16
24
32
40
V
GS,
Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
Q
G
, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S16-0754-Rev. E, 02-May-16
Document Number: 91064
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF830S, SiHF830S, IRF830L, SiHF830L
www.vishay.com
Vishay Siliconix
5.0
I
SD
, Reverse Drain Current (A)
10
1
4.0
150
°
C
I
D
, Drain Current (A)
V
GS
= 0 V
1.0
1.2
91064_09
3.0
2.0
10
0
25
°
C
1.0
0.0
0.4
91064_07
0.6
0.8
25
50
75
100
125
150
V
SD
, Source-to-Drain Voltage (V)
T
C
, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
R
D
10
2
5
2
Operation in this area limited
by R
DS(on)
10
µs
100
µs
1
ms
10
ms
R
g
V
DS
V
GS
I
D
, Drain Current (A)
10
5
2
D.U.T.
+
- V
DD
1
5
2
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
0.1
5
2
Fig. 10a - Switching Time Test Circuit
T
C
= 25
°C
T
J
= 150
°C
Single Pulse
2
5
10
-2
0.1
91064_08
V
DS
2
5
2
10
3
5
1
2
5
10
2
5
10
2
10
4
90 %
V
DS
, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 10b - Switching Time Waveforms
10
Thermal Response (Z
thJC
)
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
(Thermal Response)
P
DM
t
1
t
2
Notes:
1. Duty Factor, D = t
1
/t
2
2. Peak T
j
= P
DM
x Z
thJC
+ T
C
10
-2
0.1
1
10
0.1
10
-2
10
-5
91064_11
10
-4
10
-3
t
1
, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S16-0754-Rev. E, 02-May-16
Document Number: 91064
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF830S, SiHF830S, IRF830L, SiHF830L
www.vishay.com
Vishay Siliconix
L
Vary t
p
to obtain
required I
AS
R
g
V
DS
t
p
V
DD
D.U.T.
I
AS
10 V
t
p
0.01
Ω
I
AS
+
-
V
DD
V
DS
V
DS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
600
E
AS
, Single Pulse Energy (mJ)
500
400
300
200
100
0
V
DD
= 50 V
25
50
75
100
I
D
2.0 A
2.8 A
Bottom 4.5 A
Top
125
150
91064_12c
Starting T
J
, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
12 V
0.2 µF
0.3 µF
10 V
Q
GS
Q
G
Q
GD
D.U.T.
+
-
V
DS
V
G
V
GS
3 mA
Charge
I
G
I
D
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
S16-0754-Rev. E, 02-May-16
Document Number: 91064
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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