PD97512
IR3838MPbF
SupIRBuck
Features
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TM
HIGHLY INTEGRATED 10A
Description
The IR3838
SupIRBuck
TM
is an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard PWM controller and MOSFETs
make IR3838 a space-efficient solution, providing
accurate power delivery for low output voltage
applications.
IR3838 is a versatile regulator which offers
programmability of switching frequency and
current limit while operates in wide input and
output voltage range.
The switching frequency is programmable from
250kHz to 1.5MHz for an optimum solution.
It also features important protection functions,
such as Pre-Bias startup, hiccup current limit and
thermal shutdown to give required system level
security in the event of fault conditions.
IR3838 offers margining capability through Vref
pin. During the margining operation, PGood
tracks Vref via feedback to ensure correct status
of the output voltage.
The internal LDO enables the device to operate
from a single supply. This internal LDO can be
bypassed when an external bias voltage is
available.
SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Greater than 96% Maximum Efficiency
Single 16V Application
Single 5V Application
Wide Output Voltage Range: 0.6V to 0.9*Vin
Continuous 10A Load Capability
Programmable Switching Frequency up to 1.5MHz
Internal Digital Soft-Start
Enable Input with Voltage Monitoring Capability
Hiccup Mode Over Current Protection
Internal LDO
External Synchronization
Enhanced PreBias Start up
External Reference for Margining Purposes
Input for Tracking Applications
Integrated MOSFET Drivers and Bootstrap Diode
Operating Junction Temp: -40
o
C <Tj<125
o
C
Thermal Shut Down
Power Good Output with tracking capability
Over Voltage Detection Feature
Pin Compatible with 6A and 14A Versions
Small Size 5mmx6mm PQFN, 0.9 mm Height
Lead-free, Halogen-free and RoHS Compliant
Applications
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Netcom and Telecom Applications
Data Center Applications
Distributed Point of Load Power Architectures
Fig. 1. Typical application diagram
Rev 1.41
1
IR3838MPbF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
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PVin, Vin
……………………………………………… -0.3V to 25V
Vcc/LDO_out ……………….……..……..……….…… -0.3V to 8V
(Note2)
Boot
SW
……………………………………..……….….. -0.3V to 33V
…………………………………………..……… -0.3V to 25V (DC), -4V to 25V (AC, 100ns)
……..…………………………… …..…. -0.3V to Vcc+0.3V
(Note1)
Boot to SW
OCset
…………………………………………..…… -0.3V to 30V
………………………………... ... -0.3V to Vcc+0.3V
(Note1)
Input / output Pins
PGnd to Gnd ……………...………………….…….…. -0.3V to +0.3V
Storage Temperature Range .................................... -55°C To 150°C
Junction Temperature Range ................................... -40°C To 150°C
(Note2)
ESD Classification …………………………… ……… JEDEC(2KV)
Moisture sensitivity level………………...……………. JEDEC Level 2 @260 °C (Note
5)
Note1:
Must not exceed 8V
Note2:
Vcc must not exceed 7.5V for Junction Temperature between -10
o
C and -40
o
C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of the specifications are not implied.
Package Information
5mm x 6mm Power QFN
(Top View)
11
13
PVin
12
SW
PGnd
θ
JA
=
35
o
C / W
θ
J
-
PCB
=
2
o
C / W
Boot
Enable
Vp
14
15
16
1
2
3
4
5
6
17
Gnd
10
9
8
7
Vcc/LDO_out
Vin
Sync
Fb Vref Comp Gnd
Rt OCset PGood
ORDERING INFORMATION
PACKAGE
DESIGNATOR
M
M
Rev 1.41
PACKAGE
DESCRIPTION
IR3838MTRPbF
IR3838MTR1PbF
PIN
COUNT
17
17
PARTS PER
REEL
4000
750
2
IR3838MPbF
Block Diagram
Fig. 2. Simplified block diagram of the IR3838
Rev 1.41
3
IR3838MPbF
Pin Description
Pin Name
1
2
3
4
5
6
7
Fb
Vref
Comp
Gnd
Rt
OCset
PGood
Description
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator via resistor divider to set the output voltage and
provide feedback to the error amplifier
External reference voltage, can be used for margining operation. A
100nF capacitor should be connected between this pin and Gnd.
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to Fb to provide loop compensation
Signal ground for internal reference and control circuitry
Use an external resistor from this pin to Gnd to set the switching
frequency
Current limit set point. A resistor from this pin to SW pin will set the
current limit threshold
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to Vcc
External Synchronization, this pin is used to synchronize the device’s
switching with an external clock. It is recommended that the external
Sync clock be set to 20% above the free-running frequency. If not used,
this pin can be left floating.
Input voltage for Internal LDO. A 1.0µF capacitor should be connected
between this pin and PGnd. If external supply is connected to
Vcc/LDO_out pin, this pin should be left floating.
Input Bias Voltage, output of internal LDO. Place a minimum 2.2µF cap
from this pin to PGnd
Power Ground. This pin serves as a separated ground for the MOSFET
drivers and should be connected to the system’s power ground plane.
Switch node. This pin is connected to the output inductor
Input voltage for power stage
Supply voltage for high side driver, a 100nF capacitor should be
connected between this pin and SW pin.
Enable pin to turn on and off the device, if this pin is connected to PVin
pin through a resistor divider, input voltage UVLO can be implemented.
Input to error amplifier for tracking purposes
Signal ground for internal reference and control circuitry
8
Sync
9
10
11
12
13
14
15
16
17
Vin
V
CC
/LDO_out
PGnd
SW
PVin
Boot
Enable
Vp
Gnd
Rev 1.41
4
IR3838MPbF
Recommended Operating Conditions
Symbol
PVin
Vin
Vcc/LDO_out
Boot to SW
V
o
I
o
Fs
T
j
Definition
Input Voltage for power stage
Input Voltage for internal LDO *
Supply Voltage *
Supply Voltage
Output Voltage
Output Current
Switching Frequency
Junction Temperature
Min
1.5
7.0
4.5
4.5
0.6
0
225
-40
Max
16
16
6.5
7.5
0.9*Vin
10
1650
125
Units
V
A
kHz
o
C
* Vcc/LDO_out can be connected to an external regulated supply (≈ 5V). If so, the Vin input should be
left unconnected.
Electrical Specifications
Unless otherwise specified, these specification apply over, 7.0V<V
in
=PVin<16V, Vref=0.6V
in 0
o
C<T
j
< 125
o
C. Typical values are specified at T
a
= 25
o
C.
PARAMETER
POWER STAGE
Power Losses
Top Switch
Bottom Switch
Bootstrap Diode Forward
Voltage
SW leakage Current
Isw
SYMBOL
P
loss
R
ds(on)_Top
R
ds(on)_Bot
TEST CONDITION
V
in
=12V, V
o
=1.8V, I
o
=10A,
Fs=600kHz, L=0.6uH,
Note4
V
Boot
-V
sw
=5.0V,
I
D
=10A,Tj=25C
V
cc
=5.0V, I
D
=10A
I(Boot)= 30mA
SW=0V, Enable=0V
SW=0V, Enable=high, Vp=0V
V
in
SUPPLY CURRENT
Supply Current (Standby)
I
in(Standby)
I
in(Dyn)
Enable low , No Switching,
Enable high, Fs=500kHz,
Vin=12V
Vin(min)=7.0V, Io=0-50mA,
Cload=2.2uF
Io=50mA, Cload=2.2uF
4.7
12
180
MIN
TYP
2
17.1
8.5
260
26
11
470
6
14
400
µA
mΩ
mV
MAX
UNIT
W
µA
mA
V
in
Supply Current (Dyn)
INTERNAL REGULATOR (LDO)
Output Voltage
IntVcc Dropout
Short Circuit Current
IntVcc
IntVcc_drop
Ishort
5.2
50
70
5.7
150
V
mV
mA
INTERNAL DIGITAL SOFT START
Soft Start Clock Frequency
Soft Start Ramp Rate
Clk(SS)
Ramp(SS)
Note4
168
200
0.2
254
kHz
mV/us
Rev 1.41
5
NXP MCU
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