GS816V73C-200
209-Pin BGA
Commercial Temp
Industrial Temp
256K x 72
18Mb S/DCD Sync Burst SRAM
Supplemental Datasheet
200 MHz
1.8 V V
DD
1.8 V I/O
Functional Description
The GS816V73C-200 complies with all specifications of the
GS816273C-250/225/200, Revision 1.01, 12/2002 (attached),
except where superceded by the following tables:
• Absolute Maximum Ratings
• Power supply Ranges
• V
DDQ
Range Logic Levels
• Operating Currents
• JTAG Port Recommended Operating Conditions
• Ordering Information
• Datasheet Revision History
Current Consumption
-200
Pipeline
3-1-1-1
1.8 V
t
KQ
tCycle
Curr
(x72)
3.0
5.0
340
Unit
ns
ns
mA
Features
• 1.8 V core power supply
• 1.8 V I/O supply
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
V
DD
V
DDQ
V
CK
V
I/O
V
IN
I
IN
I
OUT
P
D
T
STG
T
BIAS
Description
Voltage on V
DD
Pins
Voltage in V
DDQ
Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
Temperature Under Bias
Value
–0.5
to 3.6
–0.5
to 3.6
–0.5
to 3.6
–0.5
to V
DDQ
+0.5 (≤ 3.6 V max.)
–0.5
to V
DD
+0.5 (≤ 3.6 V max.)
+/–20
+/–20
1.5
–55
to 125
–55
to 125
Unit
V
V
V
V
V
mA
mA
W
o
C
o
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Condi-
tions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Rev: 1.02 12/2002
1/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS816V73C-200
Power Supply Voltage Ranges
Parameter
1.8 V Supply Voltage
1.8 V V
DDQ
I/O Supply Voltage
Symbol
V
DD
V
DDQ
Min.
1.7
1.7
Typ.
1.8
1.8
Max.
2.0
2.0
Unit
V
V
Notes
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be
–2
V > Vi < V
DDn
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
V
DDQ
Range Logic Levels
Parameter
V
DD
Input High Voltage
V
DD
Input Low Voltage
V
DDQ
I/O Input High Voltage
V
DDQ
I/O Input Low Voltage
Symbol
V
IH
V
IL
V
IHQ
V
ILQ
Min.
0.6*V
DD
–0.3
0.6*V
DD
–0.3
Typ.
—
—
—
—
Max.
V
DD
+ 0.3
0.3*V
DD
V
DDQ
+ 0.3
0.3*V
DD
Unit
V
V
V
V
Notes
1
1
1,3
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be
–2
V > Vi < V
DDn
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Rev: 1.02 12/2002
2/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816V73C-200
Operating Currents
-200
Parameter
Operating
Current
1.8 V
Standby
Current
Deselect
Current
Test Conditions
Device Selected;
All other inputs
≥V
IH
or
≤
V
IL
Output open
ZZ
≥
V
DD
– 0.2 V
Device Deselected;
All other inputs
≥
V
IH
or
≤
V
IL
Mode
Symbol
0
to 70°C
290
60
35
75
–40
to 85°C
300
60
45
80
Unit
(x72)
Pipeline
I
DD
I
DDQ
I
SB
I
DD
mA
—
—
Pipeline
Pipeline
mA
mA
Notes:
1. I
DD
and I
DDQ
apply to V
DD
and V
DDQ
operation.
2. All parameters listed are worst case scenario.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
1.8 V Test Port Input High Voltage
1.8 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
Symbol
V
IHJ
V
ILJ
I
INHJ
I
INLJ
I
OLJ
V
OHJ
V
OLJ
V
OHJC
V
OLJC
Min.
0.6 * V
DD
–0.3
–300
–1
–1
1.2
—
V
DDQ
– 100 mV
—
Max.
V
DD
+0.3
0.3 * V
DD
1
100
1
—
0.4
—
100 mV
Unit Notes
V
V
uA
uA
uA
V
V
V
V
1
1
2
3
4
5, 6
5, 7
5, 8
5, 9
Notes:
1. Input Under/overshoot voltage must be
–2
V > Vi < V
DDn
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
2.
V
ILJ
≤
V
IN
≤
V
DD
3.
0 V
≤
V
IN
≤
V
ILJ
4. Output Disable, V
OUT
= 0 to V
DD
5. The TDO output driver is served by the V
DDQ
supply.
6. I
OHJ
=
–4
mA
7. I
OLJ
= + 4 mA
8. I
OHJC
= –100 uA
9. I
OHJC
= +100 uA
Rev: 1.02 12/2002
3/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816V73C-200
Ordering Information for GSI Synchronous Burst RAMs
Org
256K x 72
256K x 72
Part Number
1
Type
S/DCD Pipeline
S/DCD Pipeline
Package
209 BGA
209 BGA
Speed
2
(MHz)
200
200
T
A3
C
I
Status
GS816V73C-200
GS816V73C-200I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816V73C-200IT.
2. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
816V73_r1
816V73_r1; 816V73_r1_01
Content
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
• Removed 250 MHz and 225 MHz speed bins
• Updated tKQ from 2.5 ns to 3.0 ns
• Updated base datasheet reference
• Updated I
DDQ
values
• Updated Note 1 for Operating Currents table (should only
reference V
DD
and V
DDQ
)
• Update Note 1 for JTAG Operating Conditions table (changed
4.6 V to 3.6 V
• Added industrial part ordering information
816V73_r1_01;
816V73_r1_02
Content
Rev: 1.02 12/2002
4/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
209-Pin BGA
Commercial Temp
Industrial Temp
Features
256K x 72
18Mb S/DCD Sync Burst SRAMs
Byte Write and Global Write
250 MHz–133MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 209-bump BGA package
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
3.3 V
2.5 V
t
KQ
tCycle
Curr (x72)
Curr (x72)
2.6
4.0
430
410
2.6
4.4
2.6
5.0
2.9
6.0
3.3
6.7
3.5
7.5
ns
ns
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
395 350 300 270 245 mA
380 335 290 260 235 mA
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
Functional Description
Applications
The GS816273C is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
The GS816273C operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Controls
SCD and DCD Pipelined Reads
The GS816273C is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
Rev: 1.01 12/2002
1/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
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