128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT4HTF1664A – 128MB
1
MT4HTF3264A – 256MB
MT4HTF6464A – 512MB
For the latest component data sheet, refer to Micron's Web site:
www.micron.com
Features
• 240-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300 or PC2-6400
• 128MB (16 Meg x 64), 256MB (32 Meg x 64),
512MB (64 Meg x 64)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
240-Pin UDIMM (MO-237 R/C C)
PCB height 30.0mm (1.18in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
C
≤
+85°C)
–
Industrial (–40°C
≤
T
C
≤
+95°C)
2, 3, 4
• Package
–
240-pin DIMM (Pb-free)
• Frequency/CAS latency
–
2.5ns @ CL = 5 (DDR2-800)
4
–
2.5ns @ CL = 6 (DDR2-800)
4
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
3
–
5.0ns @ CL = 3 (DDR2-400)
3
• PCB height
–
30mm (1.18in)
Marking
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. End of life.
2. Contact Micron for industrial temperature
module offerings.
3. Contact Micron for product availability.
4. Not available in 128MB module density.
Table 1:
Speed
Grade
-80E
-800
-667
-53E
-40E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
–
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
533
533
400
CL = 3
–
–
400
400
400
t
RCD
t
RP
t
RC
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef80ed6fda/Source: 09005aef80ed6fb0
HTF4C16_32_64x64A.fm - Rev. F 4/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
Addressing
128MB
8K
8K (A0–A12)
4 (BA0, BA1)
1KB
256Mb (16 Meg x 16)
512 (A0–A8))
1 (S0#)
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
2KB
512Mb (32 Meg x 16)
1K (A0–A9)
1 (S0#)
512MB
8K
8K (A0–A12)
8 (BA0–BA2)
2KB
1Gb (64 Meg x 16)
1K (A0–A9)
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 128MB Modules
Base device: MT47H16M16,
1
256Mb DDR2 SDRAM
Module
Density
128MB
128MB
128MB
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
2
MT4HTF1664AY-667__
MT4HTF1664AY-53E__
MT4HTF1664AY-40E__
Configuration
16 Meg x 64
16 Meg x 64
16 Meg x 64
Table 4:
Part Numbers and Timing Parameters – 256MB Modules
Base device: MT47H32M16,
1
512Mb DDR2 SDRAM
Module
Density
256MB
256MB
256MB
256MB
256MB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
2
MT4HTF3264A(I)Y-80E__
MT4HTF3264A(I)Y-800__
MT4HTF3264A(I)Y-667__
MT4HTF3264A(I)Y-53E__
MT4HTF3264A(I)Y-40E__
Configuration
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
Table 5:
Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M16,
1
1Gb DDR2 SDRAM
Module
Density
512MB
512MB
512MB
512MB
512MB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
2
MT4HTF6464A(I)Y-80E__
MT4HTF6464A(I)Y-800__
MT4HTF6464A(I)Y-667__
MT4HTF6464A(I)Y-53E__
MT4HTF6464A(I)Y-40E__
Notes:
Configuration
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT4HTF3264AY-667E1.
PDF: 09005aef80ed6fda/Source: 09005aef80ed6fb0
HTF4C16_32_64x64A.fm - Rev. F 4/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6:
Pin Assignments
240-Pin UDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
31 DQ19
32
V
SS
33 DQ24
34 DQ25
35
V
SS
36 DQS3#
37 DQS3
38
V
SS
39 DQ26
40 DQ27
41
V
SS
42
NC
43
NC
44
V
SS
45
NC
46
NC
47
V
SS
48
NC
49
NC
50
V
SS
51 V
DD
Q
52
CKE0
53
V
DD
54 NC/BA2
1
55
NC
56 V
DD
Q
57
A11
58
A7
59
V
DD
60
A5
Notes:
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A4
V
DD
Q
A2
V
DD
V
SS
V
SS
V
DD
NC
V
DD
A10
BA0
V
DD
Q
WE#
CAS#
V
DD
Q
NC
NC
V
DD
Q
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
240-Pin UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
DD
Q
NC
V
DD
NC
NC
V
DD
Q
A12
A9
V
DD
A8
A6
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
V
DD
Q
A3
A1
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DD
Q
RAS#
S0#
V
DD
Q
ODT0
NC
V
DD
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
CK2#
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
1. Pin 54 is NC for 128MB and 256MB or BA2 for 512MB.
PDF: 09005aef80ed6fda/Source: 09005aef80ed6fb0
HTF4C16_32_64x64A.fm - Rev. F 4/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Table 7:
Symbol
ODT0
Pin Descriptions
Type
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Description
On-die termination:
ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,
DQS#, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Bank address inputs:
BA0–BA2 define to which device bank an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA0–BA2 define which mode register,
including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA2) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE command.
Serial clock for presence-detect:
SCL is used to synchronize the presence-detect data
transfer to and from the module.
Presence-detect address inputs:
These pins are used to configure the presence-detect
device.
Data strobe:
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only
used when differential data strobe mode is enabled via the LOAD MODE command.
Data input mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
Power supply:
1.8V ±0.1V.
SSTL_18 reference voltage.
Ground.
Serial EEPROM positive power supply:
+1.7V to +3.6V.
No connect:
These pins should be left unconnected.
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
CKE0
S0#
RAS#, CAS#, WE#
BA0, BA1
(128MB, 256MB)
BA0–BA2
(512MB)
A0–A12
Input
(SSTL_18)
SCL
SA0–SA2
DQS0–DQS7,
DQS0#–DQS7#
DM0–DM7
Input
(SSTL_18)
Input
(SSTL_18)
I/O
(SSTL_18)
I/O
(SSTL_18)
SDA
V
DD
/V
DD
Q
V
REF
V
SS
V
DDSPD
NC
I/O
(SSTL_18)
Supply
Supply
Supply
Supply
–
PDF: 09005aef80ed6fda/Source: 09005aef80ed6fb0
HTF4C16_32_64x64A.fm - Rev. F 4/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S0#
V
SS
CS#
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQS#
LDQ
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS#
LDQ
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
DQS5
DQS5#
DM5
U3
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS#
UDQ
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS#
UDQ
UDM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS#
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
LDQS#
LDQ
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS#
LDQ
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
DQS7
DQS7#
DM7
U4
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
UDQS#
UDQ
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS#
UDQ
UDM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
BA0–BA1/BA2
A0–A12
RAS#
CAS#
WE#
CKE0
V
SS
BA0–BA1/BA2: DDR2 SDRAM
A0–A12: DDR2 SDRAM
V
DD
/V
DD
Q
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
V
REF
WE#: DDR2 SDRAM
V
SS
CKE0: DDR2 SDRAM
V
DDSPD
SPD EEPROM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
SCL
U5
SPD EEPROM
WP A0
A1
A2
V
SS
SA0 SA1 SA2
CK0
CK0#
SDA
CK1
CK1#
DDR SDRAM x 2
CK2
CK2#
DDR SDRAM x 2
ODT0
V
SS
ODT0: DDR2 SDRAM
PDF: 09005aef80ed6fda/Source: 09005aef80ed6fb0
HTF4C16_32_64x64A.fm - Rev. F 4/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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