DISCRETE SEMICONDUCTORS
DATA SHEET
BF1100; BF1100R
Dual-gate MOS-FETs
Product specification
File under Discrete Semiconductors, SC07
1995 Apr 25
Philips Semiconductors
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
FEATURES
•
Specially designed for use at 9 to 12 V supply voltage
•
Short channel transistor with high forward transfer
admittance to input capacitance ratio
•
Low noise gain controlled amplifier up to 1 GHz
•
Superior cross-modulation performance during AGC.
APPLICATIONS
•
VHF and UHF applications such as television tuners and
professional communications equipment.
DESCRIPTION
Enhancement type field-effect transistor in a plastic
microminiature SOT143 or SOT143R package. The
transistor consists of an amplifier MOS-FET with source
BF1100; BF1100R
and substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
PINNING
PIN
1
2
3
4
SYMBOL
s, b
d
g
2
g
1
source
drain
gate 2
gate 1
DESCRIPTION
handbook, halfpage
d
3
d
handbook, halfpage
4
3
4
g2
g1
1
Top view
g2
g
1
2
MAM124
2
s,b
Top view
1
MAM125 - 1
s,b
BF1100 marking code:
M56.
BF1100R marking code:
M57.
Fig.1 Simplified outline (SOT143) and symbol.
Fig.2 Simplified outline (SOT143R) and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
y
fs
C
ig1-s
C
rs
F
1995 Apr 25
drain current
total power dissipation
operating junction temperature
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
f = 1 MHz
f = 800 MHz
2
PARAMETER
drain-source voltage
CONDITIONS
−
−
−
−
24
−
−
−
MIN.
−
−
−
−
28
2.2
25
2
TYP.
MAX.
14
30
200
150
33
2.6
35
−
UNIT
V
mA
mW
°C
mS
pF
fF
dB
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
I
D
I
G1
I
G2
P
tot
PARAMETER
drain-source voltage
drain current
gate 1 current
gate 2 current
total power dissipation
BF1100
BF1100R
T
stg
T
j
Note
1. Device mounted on a printed-circuit board.
storage temperature
operating junction temperature
see Fig.3
up to T
amb
= 50
°C;
note 1
up to T
amb
= 40
°C;
note 1
−
−
−65
−
CONDITIONS
−
−
−
−
BF1100; BF1100R
MIN.
MAX.
14
30
±10
±10
200
200
+150
+150
V
UNIT
mA
mA
mA
mW
mW
°C
°C
MLD155
MLD156
handbook, halfpage
250
40
Y fs
(mS)
30
Ptot
(mW)
200
150
20
BF1100R
100
BF1100
10
50
0
0
50
100
150
200
o
Tamb ( C)
0
50
0
50
100
150
T j ( C)
o
Fig.4
Fig.3 Power derating curves.
Forward transfer admittance as a function
of junction temperature; typical values.
1995 Apr 25
3
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
BF1100
BF1100R
R
th j-s
thermal resistance from junction to soldering point
BF1100
BF1100R
Notes
1. Device mounted on a printed-circuit board.
2. T
s
is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
T
j
= 25
°C;
unless otherwise specified.
SYMBOL
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
PARAMETER
gate 1-source breakdown voltage
gate 2-source breakdown voltage
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
CONDITIONS
V
G2-S
= V
DS
= 0; I
G1-S
= 1 mA
V
G1-S
= V
DS
= 0; I
G2-S
= 1 mA
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
V
G2-S
= 4 V; V
DS
= 9 V;
I
D
= 20
µA
V
G2-S
= 4 V; V
DS
= 12 V;
I
D
= 20
µA
V
G2-S(th)
gate 2-source threshold voltage
V
G1-S
= 4 V; V
DS
= 9 V;
I
D
= 20
µA
V
G1-S
= 4 V; V
DS
= 12 V;
I
D
= 20
µA
I
DSX
drain-source current
V
G2-S
= 4 V; V
DS
= 9 V;
R
G1
= 180 kΩ; note 1
V
G2-S
= 4 V; V
DS
= 12 V;
R
G1
= 250 kΩ; note 2
I
G1-SS
I
G2-SS
Notes
1. R
G1
connects gate 1 to V
GG
= 9 V; see Fig.27.
2. R
G1
connects gate 1 to V
GG
= 12 V; see Fig.27.
gate 1 cut-off current
gate 2 cut-off current
V
G2-S
= V
DS
= 0; V
G1-S
= 12 V
V
G1-S
= V
DS
= 0; V
G2-S
= 12 V
note 2
T
s
= 92
°C
T
s
= 78
°C
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
note 1
BF1100; BF1100R
VALUE
500
550
290
360
UNIT
K/W
K/W
K/W
K/W
MIN.
13.2
13.2
0.5
0.5
0.3
0.3
0.3
0.3
8
8
−
−
MAX.
20
20
1.5
1.5
1
1
1.2
1.2
13
13
50
50
V
V
V
V
V
V
V
V
UNIT
mA
mA
nA
nA
1995 Apr 25
4
Philips Semiconductors
Product specification
Dual-gate MOS-FETs
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
°C;
V
G2-S
= 4 V; I
D
= 10 mA; unless otherwise specified.
SYMBOL
y
fs
PARAMETER
forward transfer admittance
CONDITIONS
pulsed; T
j
= 25
°C
V
DS
= 9 V
V
DS
= 12 V
C
ig1-s
input capacitance at gate 1
f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
C
ig2-s
input capacitance at gate 2
f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
C
os
drain-source capacitance
f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
C
rs
reverse transfer capacitance f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
F
noise figure
f = 800 MHz; G
S
= G
Sopt
; B
S
= B
Sopt
V
DS
= 9 V
V
DS
= 12 V
−
−
−
−
−
−
−
−
−
−
24
24
BF1100; BF1100R
MIN.
TYP.
28
28
2.2
2.2
1.6
1.4
1.4
1.1
25
25
2
2
MAX.
33
33
2.6
2.6
−
−
1.8
1.5
35
35
2.8
2.8
UNIT
mS
mS
pF
pF
pF
pF
pF
pF
fF
fF
dB
dB
MLD157
0
handbook, halfpage
gain
reduction
(dB)
10
handbook, halfpage
120
MLD158
Vunw
(dBµV)
110
(1)
(2)
20
100
30
90
40
50
0
1
2
3
VAGC (V)
4
80
0
10
20
30
40
50
gain reduction (dB)
f = 50 MHz.
T
j
= 25
°C.
(1) R
G
= 250 kΩ to V
GG
= 12 V
(2) R
G
= 180 kΩ to V
GG
= 9 V
f
w
= 50 MHz; f
unw
= 60 MHz; T
amb
= 25
°C.
Fig.6
Fig.5
Gain reduction as a function of the AGC
voltage; typical values.
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.27.
1995 Apr 25
5
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