HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
IDT70V3569S
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
◆
◆
◆
◆
◆
◆
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
Grid Array
Green parts availble, see ordering instructions
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B
W
0
L
B
W
1
L
B
W
2
L
B B
WW
3 3
L R
BB
WW
2 1
RR
B
W
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
16K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
13L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
13R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4831 tbl 01
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC 4831/12
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V3569 is a high-speed 16K x 36 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times. With an input data register, the IDT70V3569 has been
optimized for applications having unidirectional or bidirectional data flow
in bursts. An automatic power down feature, controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to enter a very low standby power
mode.
The 70V3569 can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (V
DD
) remains at 3.3V.
Pin Configuration
(1,2,3,4)
12/12/01
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
IO
19L
IO
18L
B1
B2
V
SS
B3
NC
B4
NC
B5
NC
B6
A
12L
B7
A
8L
B8
BE
1L
B9
V
DD
B10
CLK
L
CNTEN
L
A
4L
B11
B12
B13
A
0L
B14
OPT
L
I/O
17L
B15
B16
V
SS
B17
I/O
20R
C1
V
SS
C2
I/O
18R
C3
V
SS
C4
NC
C5
A
13L
C6
A
9L
C7
BE
2L
C8
CE
0L
C9
V
SS
C10
ADS
L
C11
A
5L
C12
A
1L
C13
V
SS
C14
V
DDQR
I/O
16L
I/O
15R
C15
C16
C17
V
DDQL
I/O
19R
V
DDQR
V
DD
D1
D2
D3
D4
NC
D5
NC
D6
A
10L
D7
BE
3L
D8
CE
1L
D9
V
SS
D10
R/W
L
D11
A
6L
D12
A
2L
D13
V
DD
D14
I/O
16R
I/O
15L
D15
D16
V
SS
D17
I/O
22L
E1
V
SS
E2
I/O
21L
I/O
20L
E3
E4
NC
A
11L
A
7L
BE
0L
V
DD
OE
L
CNTRST
L
A
3L
V
DD
I/O
17R
V
DDQL
I/O
14L
I/O
14R
E14
E15
E16
E17
I/O
23L
I/O
22R
V
DDQR
I/O
21R
F1
F2
F3
F4
I/O
12L
I/O
13R
F14
F15
V
SS
F16
I/O
13L
F17
V
DDQL
I/O
23R
I/O
24L
G1
G2
G3
V
SS
G4
V
SS
G14
I/O
12R
I/O
11L
V
DDQR
G15
G16
G17
I/O
26L
V
SS
H1
H2
I/O
25L
I/O
24R
H3
H4
I/O
9L
V
DDQL
I/O
10L
I/O
11R
V
DD
J1
I/O
26R
V
DDQR
I/O
25R
J2
J3
J4
70V3569BF
BF-208
(5)
208-Pin fpBGA
Top View
(6)
H14
H15
H16
H17
V
DD
J14
IO
9R
J15
V
SS
J16
I/O
10R
J17
V
DDQL
K1
V
DD
K2
V
SS
K3
V
SS
K4
V
SS
K14
V
DD
K15
V
SS
V
DDQR
K16
K17
I/O
28R
L1
V
SS
L2
I/O
27R
L3
V
SS
L4
I/O
7R
V
DDQL
I/O
8R
L14
L15
L16
V
SS
L17
I/O
29R
I/O
28L
V
DDQR
I/O
27L
M1
M2
M3
M4
I/O
6R
M14
I/O
7L
M15
V
SS
M16
I/O
8L
M17
V
DDQL
I/O
29L
I/O
30R
N1
N2
N3
V
SS
N4
V
SS
N14
I/O
6L
N15
I/O
5R
V
DDQR
N16
N17
I/O
31L
P1
V
SS
P2
I/O
31R
I/O
30L
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
I/O
3R
V
DDQL
I/O
4R
P14
P15
P16
I/O
5L
P17
I/O
32R
I/O
32L
V
DDQR
I/O
35R
R1
R2
R3
R4
NC
R5
NC
R6
A
12R
R7
A
8R
R8
BE
1R
R9
V
DD
R10
CLK
R
CNTEN
R
A
4R
R11
R12
R13
I/O
2L
R14
I/O
3L
R15
V
SS
R16
I/O
4L
R17
V
SS
T1
I/O
33L
I/O
34R
T2
T3
NC
T4
NC
T5
A
13R
T6
A
9R
T7
BE
2R
CE
0R
T8
T9
V
SS
T10
ADS
R
T11
A
5R
T12
A
1R
T13
V
SS
T14
V
DDQL
I/O
1R
V
DDQR
T15
T16
T17
I/O
33R
U1
I/O
34L
V
DDQL
V
SS
U2
U3
U4
NC
U5
NC
U6
A
10R
U7
BE
3R
CE
1R
U8
U9
V
SS
U10
R/W
R
A
6R
U12
A
2R
U13
V
SS
U14
I/O
0R
U15
V
SS
U16
I/O
2R
U17
V
SS
I/O
35L
V
DD
NC
NC
A
11R
A
7R
BE
0R
V
DD
OE
R
A
3R
A
0R
V
DD
OPT
R
I/O
0L
I/O
1L
,
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
4831 drw 02c
6.42
2
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
70V3569BC
BC-256
(5)
256-Pin BGA
Top View
(6)
12/12/01
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
B1
NC
B2
NC
B3
NC
B4
NC
B5
A
11L
B6
A
8L
B7
BE
2L
B8
CE
1L
B9
OE
L
CNTEN
L
B10
B11
A
5L
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
I/O
18L
C1
NC
C2
NC
C3
NC
C4
NC
C5
A
12L
C6
A
9L
C7
BE
3L
C8
CE
0L
R/W
L
CNTRST
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
I/O
17L
C15
NC
C16
I/O
18R
I/O
19L
D1
D2
V
SS
D3
NC
D4
A
13L
D5
A
10L
D6
A
7L
D7
BE
1L
D8
BE
0L
CLK
L
ADS
L
D9
D10
D11
A
6L
D12
A
3L
D13
OPT
L
I/O
17R
I/O
16L
D14
D15
D16
I/O
20R
I/O
19R
I/O
20L
E1
E2
E3
V
DD
E4
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E5
E6
E7
E8
E9
E10
E11
E12
E13
I/O
15R
I/O
15L
I/O
16R
E14
E15
E16
I/O
21R
I/O
21L
I/O
22L
V
DDQL
F1
F2
F3
F4
V
DD
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
I/O
13L
I/O
14L
I/O
14R
F12
F13
F14
F15
F16
I/O
23L
I/O
22R
I/O
23R
V
DDQL
G1
G2
G3
G4
V
DD
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
G12
V
DDQR
I/O
12R
I/O
13R
I/O
12L
G13
G14
G15
G16
I/O
24R
I/O
24L
I/O
25L
V
DDQR
H1
H2
H3
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
10L
I/O
11L
I/O
11R
H13
H14
H15
H16
I/O
26L
I/O
25R
J1
J2
I/O
26R
V
DDQR
V
SS
J3
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
I/O
9R
J13
J14
IO
9L
I/O
10R
J15
J16
I/O
27L
I/O
28R
I/O
27R
V
DDQL
K1
K2
K3
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
DDQR
I/O
8R
I/O
7R
K13
K14
K15
I/O
8L
K16
I/O
29R
I/O
29L
I/O
28L
V
DDQL
L1
L2
L3
L4
V
SS
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
I/O
6R
L13
L14
I/O
6L
L15
I/O
7L
L16
I/O
30L
I/O
31R
I/O
30R
V
DDQR
M1
M2
M3
M4
V
DD
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
5L
M13
M14
I/O
4R
I/O
5R
M15
M16
I/O
32R
I/O
32L
I/O
31L
V
DDQR
N1
N2
N3
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
3R
N13
N14
I/O
3L
N15
I/O
4L
N16
I/O
33L
I/O
34R
I/O
33R
P1
P2
P3
V
DD
P4
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P5
P6
P7
P8
P9
P10
P11
P12
V
DD
P13
I/O
2L
P14
I/O
1R
I/O
2R
P15
P16
I/O
35R
I/O
34L
R1
R2
NC
R3
NC
R4
A
13R
R5
A
10R
R6
A
7R
R7
BE
1R
BE
0R
CLK
R
ADS
R
R8
R9
R10
R11
A
6R
R12
A
3R
R13
I/O
0L
I/O
0R
R14
R15
I/O
1L
R16
I/O
35L
T1
NC
T2
NC
T3
NC
T4
NC
T5
A
12R
T6
A
9R
T7
BE
3R
CE
0R
R/W
R
CNTRST
R
T8
T9
T10
T11
A
4R
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
NC
NC
NC
NC
A
11R
A
8R
BE
2R
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
4831 drw 02d
,
6.42
3
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
12/12/01
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
V
SS
V
DDQR
I/O
18R
I/O
18L
V
SS
V
DD
V
SS
NC
NC
NC
NC
NC
NC
NC
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
BE
3L
BE
2L
BE
1L
BE
0L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
CNTRST
L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
V
DD
V
DD
V
SS
OPT
L
I/O
17L
I/O
17R
V
DDQR
V
SS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
19L
I/O
19R
I/O
20L
I/O
20R
V
DDQL
V
SS
I/O
21L
I/O
21R
I/O
22L
I/O
22R
V
DDQR
V
SS
I/O
23L
I/O
23R
I/O
24L
I/O
24R
V
DDQL
V
SS
I/O
25L
I/O
25R
I/O
26L
I/O
26R
V
DDQR
V
SS
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
27R
I/O
27L
I/O
28R
I/O
28L
V
DDQR
V
SS
I/O
29R
I/O
29L
I/O
30R
I/O
30L
V
DDQL
V
SS
I/O
31R
I/O
31L
I/O
32R
I/O
32L
V
DDQR
V
SS
I/O
33R
I/O
33L
I/O
34R
I/O
34L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70V3569DR
DR-208
(5)
208-Pin PQFP
Top View
(6)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
I/O
16L
I/O
16R
I/O
15L
I/O
15R
V
SS
V
DDQL
I/O
14L
I/O
14R
I/O
13L
I/O
13R
V
SS
V
DDQR
I/O
12L
I/O
12R
I/O
11L
I/O
11R
V
SS
V
DDQL
I/O
10L
I/O
10R
I/O
9L
I/O
9R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
V
SS
V
DDQL
I/O
8R
I/O
8L
I/O
7R
I/O
7L
V
SS
V
DDQR
I/O
6R
I/O
6L
I/O
5R
I/O
5L
V
SS
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
,
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
V
SS
V
DDQL
I/O
35R
I/O
35L
V
DD
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
BE
3R
BE
2R
BE
1R
BE
0R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
CNTRST
R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
V
DD
V
SS
V
SS
OPT
R
I/O
0L
I/O
0R
V
DDQL
V
SS
4831 drw 02a
6.42
4
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
13L
I/O
0L
- I/O
35L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
BE
0L
-
BE
3L
V
DDQL
OPT
L
V
DD
V
SS
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
13R
I/O
0R
- I/O
35R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
BE
0R
-
BE
3R
V
DDQR
OPT
R
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe Enable
Counter Enable
Counter Reset
Byte Enables (9-bit bytes)
Power (I/O Bus)
(3.3V or 2.5V)
(1)
Option for selection V
DDQX
(1,2)
Power
(3.3V)
(1)
Ground
(0V)
4831 tbl 01
Names
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX
must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
CE
0
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CE
1
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
BE
3
X
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
L
BE
2
X
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
L
BE
1
X
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
L
BE
0
X
X
H
L
H
H
H
L
H
L
L
H
H
H
L
H
L
L
R/W
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
X
Byte 3
I/O
27-35
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
IN
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
OUT
High-Z
Byte 2
I/O
18-26
High-Z
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
High-Z
D
IN
D
IN
High-Z
High-Z
D
OUT
High-Z
High-Z
D
OUT
D
OUT
High-Z
Byte 1
I/O
9-17
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
High-Z
D
IN
High-Z
D
IN
High-Z
D
OUT
High-Z
High-Z
D
OUT
High-Z
D
OUT
High-Z
Byte 0
I/O
0-8
High-Z
High-Z
High-Z
D
IN
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
OUT
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
High-Z
MODE
Deselected–Power Down
Deselected–Power Down
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
4831 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
6.42
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
