IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
FEATURES:
DESCRIPTION:
IDT5T940
• Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• 3-level inputs for feedback divide ratio and output frequency range
selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on Q
OUT
• Regenerated input clock or Q
OUT
/4 on Q
REG
• Lock indicator
• Power-down mode
• LVPECL or LVDS outputs
• Three modes of output frequency range
- Mode 0: Q
OUT
range 155.5 - 166.6MHz. Q
REG
is a regenerated version
of the input clock.
- Mode 1: Q
OUT
range 622 - 666.5MHz. Q
REG
output 155.5-166.6MHz.
- Mode 2: Q
OUT
range 622 - 666.5MHz. Q
REG
is a regenerated version
of the input clock frequency.
• Selectable loop bandwidths
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
The three modes of output frequency range are controlled by the SELmode,
which is a 3-level pin. When SELmode is high or low, the Q
OUT
is a multiplied
version of the input clock while Q
REG
is a regenerated version of the input clock.
When SELmode is mid, the Q
OUT
is a multiplied version of the input clock while
Q
REG
is Q
OUT
/4.
The IDT5T940 features a selectable loop bandwidth.
APPLICATIONS:
•
•
•
•
•
Terabit routers
Gigabit ethernet systems
SONET / SDH systems
Digital cross connects
Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
PLLBW
1
PLLBW
0
Q
REG
PLL
DIV
N
Q
REG
CLKIN
CLKIN
INPUT
MUX
Q
OUT
DIV
M
Q
OUT
REFIN
REFIN
LOCK,
FREQ.
DETECTOR
CONTROL
LOGIC
PD
LOCK
SEL
MODE
CLK/
REF
0
CLK/
REF
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2003
Integrated Device Technology, Inc.
DECEMBER 2003
DSC 6195/23
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
Q
OUT
Q
OUT
GND
GND
V
DD
PD
V
DD
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
V
I
V
O
T
J
21
20
19
V
DD
GND
Q
REG
Q
REG
GND
V
DD
LOCK
Description
Power Supply Voltage
Input Voltage
Output Voltage
Junction Temperature
Storage Temperature
Max
–0.5 to +4.1
–0.5 to +4.1
–0.5 to V
DD
+0.5
150
–65 to +165
Unit
V
V
V
°C
°C
28
GND
CLKIN
CLKIN
GND
REFIN
REFIN
GND
1
2
3
4
5
6
7
8
27
26
25
24
23
22
T
STG
GND
18
17
16
15
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
9
10
11
12
13
14
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Typ.
2.5
—
Max.
3
—
Unit
pF
pF
SEL
MODE
V
DD
CLK/REF
1
CLK/REF
0
V
DD
PLLBW
0
PLLBW
1
VFQFPN
TOP VIEW
NOTE:
1. Capacitance applies to all inputs except CLK/REF
[1:0]
and SELmode.
RECOMMENDED OPERATING RANGE
Symbol
T
A
V
DD
V
T
Description
Ambient Operating Temperature
Power Supply Voltage
Termination Voltage (LVPECL)
Termination Voltage (LVDS)
Min.
–40
2.375
—
—
Typ.
+25
—
V
DD
– 2
1.2
Max.
+85
3.465
—
—
Unit
°C
V
V
2
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PLL BANDWIDTH SELECTION
PLLBW
[1:0]
LL
LH
HL
HH
Min.
65KHz
250KHz
1MHz
4MHz
Max.
120KHz
500KHz
2MHz
8MHz
Min. CLKIN/REFIN
19.44MHz
19.44MHz
38.88MHz
155.52MHz
OUTPUT FREQUENCY RANGE
SELmode
L
M
H
Q
OUT
/Q
OUT
155.5 - 166.6
622 - 666.5
622 - 666.5
Q
REG
/Q
REG
regenerated CLKIN/CLKIN
155.5 - 166.6
regenerated CLKIN/CLKIN
Unit
MHz
MHz
MHz
INPUT FREQUENCY RANGE
CLK/REF
[1:0]
HH
HM
HL
MH
MM
ML
LH
LM
LL
Input Frequency Range
19.4MHz - 20.9MHz
reserved
38.8MHz - 41.7MHz
77.7MHz - 83.4MHz
Automatic Detection
155.5MHz - 167MHz
311MHz - 334MHz
reserved
622MHz - 667MHz
LOCK
FREQUENCY DETECTOR
The 5T940 will lock to, and track, a valid CLKIN signal;
LOCK
will be low
when this has occurred. If CLKIN fails, the 5T940 PLL will smoothly switch
to lock to REFIN without generating any glitches on the output. The fact that
the PLL is locked to REFIN rather than CLKIN is indicated by a high state on
LOCK.
When a valid input is then applied to CLKIN, the 5T940 will smoothly
switch back to locking on CLKIN, and
LOCK
will go low.
LOCK
will also switch
to high should the frequency of CLKIN drift close to the limits of the VCO tuning
range.
PIN DESCRIPTION
Pin Name
CLKIN,
CLKIN
I/O
I
Type
Adjustable
(1)
Description
Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float
to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected
on the floating input.
Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/CLKIN fails. Differential
or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL
threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the
floating input.
3 level inputs controlling PLL feedback divider ratio. Automatic detection is used if both inputs are MID.
3 level input to select output frequency range for Q
OUT
/Q
OUT
and Q
REG
/Q
REG
(see Output Frequency Range table)
PLL Bandwidth Select Inputs (see PLL Bandwidth Selection table)
Power Down Control. Shuts off entire chip when LOW.
(3)
REFIN,
REFIN
I
Adjustable
(1)
CLK/REF
[1:0]
SELmode
PLLBW
[1:0]
PD
Q
OUT
, Q
OUT
Q
REG
, Q
REG
LOCK
V
DD
GND
I
I
I
I
0
0
0
3-level
(2)
3-level
(2)
LVTTL
LVTTL
Adjustable
LVTTL
PWR
PWR
Adjustable
(3)
Differential clock output. LVPECL or LVDS outputs.
Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs.
LOW when PLL is locked to CLKIN, HIGH in all other conditions
Power Supply
Ground
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
2. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating.
3. Outputs can be LVPECL or LVDS.
3
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION
Application
Non-FEC
REFIN (MHz)
19.44, 38.88, 77.76, 155.52, 311.04,
622.08
CKIN (MHz)
19.44
SELmode
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
Q
REG
(MHz)
19.44
155.52
19.44
38.88
155.52
38.88
77.76
155.52
77.76
155.52
155.52
155.52
311.04
155.52
311.04
622.08
155.52
622.08
20.83
166.63
20.83
41.66
166.63
41.66
83.31
166.63
83.31
166.63
166.63
166.63
333.26
166.63
333.26
666.52
166.63
666.52
Q
OUT
(MHz)
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
38.88
77.76
155.52
311.04
622.08
FEC
20.83, 41.66, 83.31, 166.63, 333.26,
666.52
20.83
41.66
83.31
166.63
333.26
666.52
4
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION (CONTINUED)
Application
10GE copper
REFIN (MHz)
19.53, 39.06, 78.12, 156.25, 312.5,
625
CKIN (MHz)
19.53
SEL mode
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
Q
REG
(MHz)
19.53
156.25
19.53
39.06
156.25
39.06
78.12
156.25
78.12
156.25
156.25
156.25
312.50
156.25
312.5
625
156.25
625
20.14
161.13
20.14
40.28
161.13
40.28
80.56
161.13
80.56
161.13
161.13
161.13
322.26
161.13
322.26
644.53
161.13
644.53
Q
OUT
(MHz)
156.25
625
625
156.25
625
625
156.25
625
625
156.25
625
625
156.25
625
625
156.25
625
625
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
39.06
78.12
156.25
312.5
625
10GE optical
20.14, 40.28, 80.56, 161.13, 322.26,
644.53
20.14
40.28
80.56
161.13
322.26
644.53
5
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