CYStech Electronics Corp.
2-Wire Serial EEPROMs 1K/2K/4K/8K/16K
Spec. No. : C705P8
Issued Date : 2007.08.23
Revised Date :
Page No. : 1/12
CTK24BC01-16P8
Description
The CTK24BC family provides 1K, 2K, 4K, 8K and 16K of serial electrically erasable and programmable
read-only memory (EEPROM). The wide Vdd range allows for low-voltage operation down to 1.8V. The
device, fabricated using traditional CMOS EEPROM technology, is optimized for many industrial and
commercial applications where low-voltage and low-power operation is essential. The device is accessed
via a 2-wire serial interface.
Features
•
Internally organized as 128×8(1K), 256×8(2K)
512×8(4K), 1024×8(8K), 2048×8(16K)
•
Low-voltage and standard-voltage operation :
1.8~5.5V
•
2-wire serial interface bus
•
Date retention : 100 years
•
High endurance : 1,000,000 write cycles
•
100kHz(1.8V)& 400kHz(5V) compatibility
•
Bi-directional data transfer protocol
•
Self-timed write cycle (5ms max)
•
Write protect pin for hardware data protection
•
8-byte page (1K, 2K) and 16-byte page (4K, 8K, 16K)
write modes
•
Allows for partial page write
Absolute Maximum Ratings
Parameter
Voltage on any pin with respect to ground
Maximum operating voltage
DC output current
Operating temperature range
Storage temperature range
Ratings
-0.8 to V
CC
+1.5
6.25
5.0
-55 ~ +125
-65 ~ +150
Unit
V
V
mA
℃
℃
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of these specifications are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
CTK24BC01-16P8
CYStek Product Specification
CYStech Electronics Corp.
Pin Configurations
Pin Name
A0-A2
SDA
SCL
WP
Gnd
V
CC
Spec. No. : C705P8
Issued Date : 2007.08.23
Revised Date :
Page No. : 2/12
Function
Address inputs
Serial data
Serial clock input
Write protect
Ground
Power supply
Block Diagram
CTK24BC01-16P8
CYStek Product Specification
CYStech Electronics Corp.
Pin Descriptions
Spec. No. : C705P8
Issued Date : 2007.08.23
Revised Date :
Page No. : 3/12
Serial Data(SDA):
The SDA pin used for sending and receiving data bits in serial mode. Since the SDA
pin is defined as an open-drain connection, a pull-up resistor is needed.
Serial Clock(SCL):
The SCL input is used to synchronize data input and output with clocked out on the
falling edge of SCL.
Device/Page Addresses(A
2
, A
1
, A
0
):
The A
2
, A
1
, and A
0
pins are used to address multiple devices on a
single bus system and should be hard-wired.
●
The CTK24BC01 and CTK24BC02 use the A
2
, A
1
and A
0
pins to provide the capability for
addressing up to eight 1K/2K devices on a single bus system (please see the Device Addressing
section for further details)
●
The CTK24BC04 uses the A
2
and A
1
inputs and a total of for 4K device may be addressed on
a single bus system. The A
0
pin is not used, but should be grounded if possible.
●
The CTK24BC08 only uses the A
2
input hardware addressing. On a single bus system, a total
of two 8K devices may be addressed. The A
0
and A
1
pins are not used, but should be grounded
if possible.
●
The CTK24BC16 does not use the device address pins, so only one device can be connected to a
single bus system. Therefore, the A
0
, A
1
, and A
2
pins are not used, but should be grounded if
possible.
Write Protect (WP):
The CTK24BC01/02/04/08/16 has a Write Protect pin that provides hardware data
protection. When connected to ground, the Write Protect pin allows for normal read/write
operations. If the WP pin is connected to V
CC
, no data can be overwritten.
Memory Organization
The internal memory organization for the CTK24BC family is arranged differently for each of the densities.
The CTK24BC01, for instance, is internally organized as 16 pages of 8 bytes each and requires a 7-bit data
word address. The CTK24BC16, on the other hand, is organized as 128 pages of 16 bytes each with an
11-bit data word address. The table below summarizes these differences.
Density
# of pages
Bytes per page
Data word address length
CTK24BC01 (1K)
16 pages
8 bytes
7 bits
CTK24BC02 (2K)
32 pages
8 bytes
8 bits
CTK24BC04 (4K)
32 pages
16 bytes
9 bits
CTK24BC08 (8K)
64 pages
16 bytes
10 bits
CTK24BC16 (16K)
128 pages
16 bytes
11 bits
Pin Capacitance
Applicable over recommended operating range :T
A
=25℃, f=1MHz, V
CC
=+1.8V
Symbol
Test Condition
Max
Unit
C
I/O
Input/Output Capacitance (SDA)
8
pF
C
IN
Input Capacitance (A
0
, A
1
,A
2
, SCL)
6
pF
Note : These parameters are characterized and not 100% tested.
Condition
V
I/O
=0V
V
IN
=0V
CTK24BC01-16P8
CYStek Product Specification
CYStech Electronics Corp.
DC Characteristics
Spec. No. : C705P8
Issued Date : 2007.08.23
Revised Date :
Page No. : 4/12
Applicable over recommended operating range: T
A
=-40~+85℃, V
CC
=+1.8V~+5.0V
(unless otherwise noted)
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current V
CC
=5.0V
Supply Current V
CC
=5.0V
Standby Current V
CC
=1.8V
Standby Current V
CC
=2.5V
Standby Current V
CC
=5.5V
Input Leakage Current
Output Leakage Current
Input Low Level (
Note 1
)
Input High Level (
Note 1
)
Output Low Level V
CC
=3.0V
Output Low Level V
CC
=3.0V
Symbol
V
CC
1
V
CC
2
V
CC
3
I
CC
I
CC
I
SB
1
I
SB
2
I
SB
3
I
LI
I
LO
V
IL
V
IH
V
OL
2
V
OL
1
Condition
READ at 100KHz
WRITE at 100KHz
V
IN
=V
CC
or V
SS
V
IN
=V
CC
or V
SS
V
IN
=V
CC
or V
SS
V
IN
=V
CC
or V
SS
V
OUT
=V
CC
or V
SS
I
OL
=2.1mA
I
OL
=0.15mA
Min.
1.8
2.7
4.5
-
-
-
-
-
-
-
-0.6
V
CC
×
0.7
-
-
Typ.
-
-
-
0.4
2.0
0.6
1.4
5.0
0.2
0.1
-
-
-
-
Max.
5.5
5.5
5.5
1.0
3.0
3.0
4.0
18
5.0
5.0
V
CC
×
0.3
V
CC
+0.5
0.4
0.2
Unit
V
V
V
mA
mA
μA
μA
μA
μA
μA
V
V
V
V
Note : V
IL
and V
IH
Max are reference only and are not tested.
AC Characteristics
Applicable over recommended operating range: T
A
=-40~+85℃, V
CC
=+1.8V~+5.0V, C
L
=1 TTL Gate & 100pF(unless otherwise noted)
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(Note 1)
Clock Low to Data Out Valid
Time the bus must be free before
A new transmission can start
(Note 1)
Start Hold Time
Start Setup Time
Data in Hold Time
Data in Setup Time
Input Rise Time
(Note 1)
Input Fall Time
(Note 1)
CTK24BC01-16P8
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
Condition
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
Min.
-
4.7
1.2
4.0
0.6
-
0.1
0.1
4.7
1.2
4.0
0.6
4.7
0.6
0
0
200
100
-
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
Max.
100
400
-
-
100
50
4.5
0.9
-
-
-
-
-
1.0
0.3
300
300
Unit
KHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
μs
ns
CYStek Product Specification
CYStech Electronics Corp.
AC Characteristics(Cont.)
Spec. No. : C705P8
Issued Date : 2007.08.23
Revised Date :
Page No. : 5/12
Applicable over recommended operating range: T
A
=-40~+85℃, V
CC
=+1.8V~+5.0V, C
L
=1TTL Gate & 100pF(unless otherwise noted)
Parameter
Stop Setup Time
Data out Hold Time
Write Cycle Time
5.0V, 25℃, Byte Mode
Symbol
t
SU.STO
t
DH
t
WR
Endurance
(Note 1)
Note: 1. This parameter is characterized and not 100% tested.
Condition
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
V
CC
=1.8V
V
CC
=2.7~5.5V
Min.
4.7
0.6
100
50
-
1M
1M
Typ.
-
-
-
-
Max.
-
-
5
5
-
Unit
μs
ns
ms
Write
Cycles
Device Operation
Clock and Data Transitions:
Transitions on the SDA pin should only occur when SCL is low(refer to the
Data Validity timing diagram in Figure 3). If the SDA pin changes when SCL is high, then the transition
will be interpreted as a START or STOP condition.
START Condition:
A START condition occurs when the SDA transitions from high to low when SCL is
high. The START signal is usually used to initiate a command(refer to the START and STOP definition
timing diagram in Fig 4)
STOP Condition:
A STOP condition occurs when the SDA transitions from low to high when SCL is high.
(refer to the START and STOP definition timing diagram in Fig 4) The STOP command will put the device
into standby mode after no acknowledgement is issued during the read sequence.
Acknowledge:
An acknowledgement is sent by pulling the SDA low to confirm that a word has been
successfully received. All addresses and data words are serially transmitted to and from the EEPROM in
8-bit words, so acknowledgements are usually issued during the 9
th
clock cycle.
Standby Mode:
Standby mode is entered when the chip is initially powered-on or after a STOP command
has been issued and any internal operations have been completed.
Memory Reset:
In the event of unexpected power or connection loss, a START condition can be issued to
restart the input command sequence. If the device is currently in write cycle mode, this command will be
ignored.
CTK24BC01-16P8
CYStek Product Specification
51单片机
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