SI4800
N-channel TrenchMOS™ logic level FET
M3D315
Rev. 02 — 17 February 2004
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
1.2 Features
s
Low gate charge
s
Low on-state resistance
s
Surface mounted package
s
Fast switching.
1.3 Applications
s
Portable appliances
s
Lithium-ion battery chargers
s
Notebook computers
s
DC-to-DC converters.
1.4 Quick reference data
s
V
DS
≤
30 V
s
P
tot
≤
2.5 W
s
I
D
≤
9 A
s
R
DSon
≤
18.5 mΩ
2. Pinning information
Table 1:
Pin
1,2,3
4
5,6,7,8
Pinning - SOT96-1 (SO-8), simplified outline and symbol
Description
source (s)
gate (g)
drain (d)
g
1
Top view
4
MBK187
Simplified outline
8
5
Symbol
d
MBB076
s
SOT96-1 (SO8)
Philips Semiconductors
SI4800
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Package
Name
SI4800
SO8
Description
plastic small outline package; 8 leads
Version
SOT96-1
Type number
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
drain-source voltage (DC)
gate-source voltage (DC)
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current
T
amb
= 25
°C;
pulsed; t
p
≤
10 s
T
amb
= 25
°C;
pulsed; t
p
≤
10 s;
Figure 2
and
3
T
amb
= 70
°C;
pulsed; t
p
≤
10 s;
Figure 2
T
amb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
amb
= 25
°C;
pulsed; t
p
≤
10 s;
Figure 1
T
amb
= 70
°C;
pulsed; t
p
≤
10 s;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
Min
-
-
-
-
-
-
-
−55
−55
-
Max
30
±20
9
7
40
2.5
1.6
+150
+150
2.3
Unit
V
V
A
A
A
W
W
°C
°C
A
Source-drain diode
9397 750 12899
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 17 February 2004
2 of 12
Philips Semiconductors
SI4800
N-channel TrenchMOS™ logic level FET
120
Pder
(%)
80
03aa11
120
Ider
(%)
80
03aa19
40
40
0
0
50
100
150
200
Tamb (
°
C)
0
0
50
100
150
200
Tamb (
°
C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of ambient temperature.
Fig 2. Normalized continuous drain current as a
function of ambient temperature.
102
ID
(A)
10
tp = 10
µ
s
Limit RDSon = VDS / ID
1 ms
03ap01
10 ms
1
DC
100 ms
10-1
10 s
10-2
10-1
1
10
VDS (V)
102
T
amb
= 25
°C;
I
DM
is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12899
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 17 February 2004
3 of 12
Philips Semiconductors
SI4800
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
R
th(j-a)
Thermal characteristics
Conditions
mounted on a printed-circuit board;
minimum footprint; t
p
≤
10 s;
Figure 4
Min Typ Max Unit
-
-
50
K/W
thermal resistance from junction to ambient
Symbol Parameter
5.1 Transient thermal impedance
102
Zth(j-amb)
δ
= 0.5
(K/W)
0.2
10
0.1
0.05
0.02
1
03af83
P
δ
=
tp
T
10-1
single pulse
tp
T
t
10-2
10-4
10-3
10-2
10-1
1
10
102
tp (s)
103
T
amb
= 25
°C
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration.
9397 750 12899
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 17 February 2004
4 of 12
Philips Semiconductors
SI4800
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
GS(th)
I
DSS
gate-source threshold voltage
drain-source leakage current
I
D
= 250
µA;
V
DS
= V
GS
;
Figure 9
V
DS
= 24 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 55
°C
I
GSS
R
DSon
I
D(on)
g
fs
Q
g(tot)
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
gate-source leakage current
drain-source on-state resistance
on-state drain current
forward transconductance
total gate charge
gate-source charge
gate-drain (Miller) charge
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 7 A; V
GS
= 0 V;
Figure 12
reverse recovery time
I
S
= 7 A; dI
S
/dt =
−100
A/µs; V
R
= 30 V;
V
GS
= 0 V
V
DD
= 15 V; I
D
= 1.5 A; V
GS
= 10 V; R
G
= 6
Ω
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 9 A;
Figure 7
and
8
V
GS
= 4.5 V; I
D
= 7 A;
Figure 7
V
DS
≥
5 V; V
GS
= 10 V
V
DS
= 15 V; I
D
= 9 A
I
D
= 8 A; V
DD
= 15 V; V
GS
= 5 V;
Figure 13
Dynamic characteristics
-
-
-
-
-
-
-
-
-
-
19
11.8
2.7
5
6
7
23
11
0.86
25
-
-
-
-
16
15
30
15
1.2
80
S
nC
nC
nC
ns
ns
ns
ns
V
ns
-
-
-
-
-
30
-
-
-
15.5
24
-
1
5
100
18.5
33
-
µA
µA
nA
mΩ
mΩ
A
0.8
-
-
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
9397 750 12899
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 17 February 2004
5 of 12
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