64MB, 128MB (x64)
144-PIN SDRAM MICRODIMM
SDRAM
MICRODIMM
Features
• JEDEC-standard, PC100, PC133, 144-pin,
MicroDIMM
• Utilizes 125 MHz and 133 MHz SDRAM
components
• 64MB (8 Meg x 64), 128MB (16 Meg x 64)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode: Standard and Low Power
• 64MB module: 64ms, 4,096-cycle refresh; 128MB
module: 64ms, 8,192-cycle refresh.
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
MT4LSDT864W – 64MB
MT4LSDT1664W – 128MB
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/moduleds
Figure 1: 144-Pin MicroDIMM (MO–214)
Table 1:
MODULE
MARKING
-13E
-133
-10E
Device Timing
PC100
CL -
t
RCD -
t
RP
2-2-2
2-2-2
2-2-2
PC133
CL -
t
RCD -
t
RP
2-2-2
3-3-3
N/A
OPTIONS
MARKING
• Self Refresh Current
Standard
Low Power
• Package
144-pin MicroDIMM (standard)
144-pin MicroDIMM (lead-free)
• Frequency/CAS Latency
133 MHz/CL = 2
133 MHz/CL = 3
100 MHz/CL = 2
NOTE:
None
L
G
Y
-13E
-133
-10E
Table 2:
Address Table
64MB
128MB
8K
4 (BA0, BA1)
8K (A0–A12)
512 (A0–A8)
1 (S0)
16 Meg x 16
4K
4 (BA0, BA1)
4K (A0–A11)
512 (A0–A8)
1 (S0)
8 Meg x 16
1. Contact Micron for availability of lead-free prod-
ucts.
Refresh Count
Device Banks
Row Addressing
Column Addressing
Module Ranks
Component
Configuration
09005aef80dc39c7
SD4C8_16x64WG_B.fm - Rev. B 9/03 EN
1
©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
64MB, 128MB (x64)
144-PIN SDRAM MICRODIMM
Table 6:
Pin Descriptions
SYMBOL
RAS#, CAS#, WE#
CK0
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input
Clock: CK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. CK also increments the
internal burst counter and controls the output registers.
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides POWER-DOWN and
SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Input
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input
Input Mask: DQMB is an input mask signal for write accesses.
Input data is masked when DQMB is sampled HIGH during a
WRITE cycle. The output buffers are placed in a High-Z state
(after a two-clock latency) when DQMB is sampled HIGH
during a READ cycle.
Input
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0 is also used to program the twelfth bit of the
Mode Register.
Input
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 is sampled
during a PRECHARGE command to determine whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Input
Serial Clock for Presence-Detect: SCL is used to synchro nize the
presence-detect data transfer to and from the module.
Input/Output Data I/Os: Data bus.
TYPE
Input
DESCRIPTION
PIN NUMBERS
65–67
61
62
CKE0
69
S0#
23–26, 115–118
DQMB0–DQMB7
106, 110
BA0, BA1
29–34, 70
(128MB),
103–105, 109, 111, 112
A0–A11
(64MB)
A0–A12
(128MB)
142
3–10, 13–20, 37–44,
47–54, 83–90, 93–100,
121–128, 131–138
141
SCL
DQ0–DQ63
SDA
11, 12, 27, 28, 45, 46,
63, 64, 81, 82, 101, 102,
113, 114, 129, 130, 143,
144
1, 2, 21, 22, 35, 36, 55,
56, 75, 76, 91, 92, 107,
108, 119, 120, 139, 140
57 –60, 70 (64MB)–74,
77–80
V
DD
Input/Output Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and data out of the presence-
detect portion of the module.
Supply
Power Supply: +3.3V ±0.3V.
V
SS
Supply
Ground.
NC
–
Not Connected: These pins are not connected on these
modules.
09005aef80dc39c7
SD4C8_16x64WG_B.fm - Rev. B 9/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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