74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
Rev. 2 — 26 January 2015
Product data sheet
1. General description
The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs
(A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three
enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and
E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to
32 lines) decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an
eight output demultiplexer by using one of the active LOW enable inputs as the data input
and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard no. 7A
Input levels:
For 74HC138-Q100: CMOS level
For 74HCT138-Q100: TTL level
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC138D-Q100
74 HCT138D-Q100
74HC138PW-Q100
74HCT138PW-Q100
74HC138BQ-Q100
74HCT138BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Functional diagram
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2015
2 of 17
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO16 and TSSOP16
Fig 5.
Pin configuration DHVQFN16
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2015
3 of 17
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
5.2 Pin description
Table 2.
Symbol
A0, A1, A2
E1, E2
E3
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7
GND
V
CC
Pin description
Pin
1, 2, 3
4, 5
6
15, 14, 13, 12, 11, 10, 9, 7
8
16
Description
address input A0, A1, A2
enable input E1, E2 (active LOW)
enable input E3 (active HIGH)
output Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 (active LOW)
ground (0 V)
positive supply voltage
6. Functional description
Table 3.
Control
E1
H
X
X
L
E2
X
H
X
L
E3
X
X
L
H
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Input
A2
X
A1
X
A0
X
Output
Y7
H
Y6
H
Y5
H
Y4
H
Y3
H
Y2
H
Y1
H
Y0
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2015
4 of 17
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
[1]
Max
+7
20
20
25
50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC138-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT138-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2015
5 of 17
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