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TSB41LV01
IEEE 1394A ONE-PORT CABLE
TRANSCEIVER/ARBITER
SLLS365A – AUGUST 1999 – REVISED NOVEMBER 2000
D
D
D
D
D
D
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D
Fully Supports Provisions of IEEE
1394-1995 Standard for High Performance
Serial Bus
†
and the P1394a Supplement
Fully Interoperable With FireWire™ and
i.LINK™ Implementation of IEEE Std 1394
Fully Compliant With OpenHCI
Requirements
Provides One P1394a Fully Compliant
Cable Port at 100/200/400 Megabits per
Second (Mbits/s)
Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume
Extended Resume Signaling for
Compatibility With Legacy DV Devices
Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Pin, Link
Interface Disable via LPS, and Inactive Port
Powered-Down
Ultralow-Power Sleep Mode
Node Power Class Information Signaling
for System Power Management
Cable Power Presence Monitoring
Cable Port Monitors Line Conditions for
Active Connection to Remote Node
D
D
D
D
D
D
D
D
D
D
D
D
Register Bits Give Software Control of
Contender Bit, Power Class bits, Link
Active Control Bit and P1394a Features
Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
Interface to Link Layer Controller Supports
Low Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation
Interoperable With Link-Layer Controllers
Using 3.3 V and 5 V Supplies
Interoperable With Other PHYsical Layers
(PHYs) Using 3.3 V and 5 V Supplies
Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
Incoming Data Resynchronized to Local
Clock
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
Single 3.3 Volt Supply Operation
Meets Intel Mobile Power Guideline 2000
Low Cost High Performance 64 Pin TQFP
(PAP) Thermally Enhanced Package
description
The TSB41LV01 provides the digital and analog transceiver functions needed to implement a two-port node in
a cable-based IEEE 1394 network. The cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV01 is designed to interface
with a link layer controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV23, TSB12LV31, TSB12LV41,
TSB12LV42, or TSB12LV01A.
The TSB41LV01 requires only an external 24.576 MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock
signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Incorporated.
i.LINK is a trademark of SONY.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TSB41LV01
IEEE 1394A ONE-PORT CABLE
TRANSCEIVER/ARBITER
SLLS365A – AUGUST 1999 – REVISED NOVEMBER 2000
description (continued)
The TSB41LV01 supports an optional isolation barrier between itself and its LLC. When the /ISO input terminal
is tied high, the LLC interface outputs behave normally. When the /ISO terminal is tied low, internal differentiating
logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer
galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement
(section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI Bus holder isolation the /ISO
terminal on the PHY must be high.
Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths
(depending on the requested transmission speed) and are latched internally in the TSB41LV01 in
synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted
at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the
outbound data-strobe information stream. During transmission, the encoded data information is transmitted
differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the
TPA cable pair(s).
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover
the receive clock signal and the serial data bits. The serial data bits are split into two, four or eight bit parallel
streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock
and sent to the associated LLC.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.
The TSB41LV01 provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. This bias
voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This
bias voltage source must be stabilized by an external filter capacitor of 1
µF.
The line drivers in the TSB41LV01 operate in a high-impedance current mode, and are designed to work with
external 112-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω
resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with
recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed
to meet the standard specifications when connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal
operating currents. This current setting resistor has a value of 6.3-kΩ
±0.5%.
This may be accomplished by
placing a 6.34-kΩ
±0.5%
resistor in parallel with a 1-MΩ resistor.
When the power supply of the TSB41LV01 is 0 V while the twisted-pair cables are connected, the TSB41LV01
transmitter and receiver circuitry will present a high impedance to the cable and will not load the TPBIAS voltage
at the other end of the cable.
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal should be connected to V
DD
, SE should be tied to ground through a 1-kΩ resistor,
while SM should be connected directly to ground.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TSB41LV01
IEEE 1394A ONE-PORT CABLE
TRANSCEIVER/ARBITER
SLLS365A – AUGUST 1999 – REVISED NOVEMBER 2000
description (continued)
Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID
packet, and are hardwired high or low as a function of the equipment design. The PC0 – PC2 terminals are used
to indicate the default power-class status for the node (the need for power from the cable or the ability to supply
power to the cable). See Table 1 for power-class encoding. The C/LKON terminal is used as an input to indicate
that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).
The TSB41LV01 supports suspend/resume as defined in the IEEE P1394a specification. The suspend
mechanism allows pairs of directly-connected ports to be placed into a low power conservation state
(suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended
state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state
is capable of detecting connection status changes and detecting incoming TPBias. When the port of the
TSB41LV01 is suspended all circuits except the bandgap reference generator and bias detection circuits are
powered down, resulting in significant power savings. For additional details of suspend/resume operation refer
to the P1394a specification. The use of suspend/resume is recommended for new designs.
The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted
high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the
port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power-down,
during reset, or when the port is disabled as commanded by the LLC.
The CNA (cable-not-active) output terminal is asserted high when there are no twisted-pair cable ports receiving
incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine
when to power down the TSB41LV01. The CNA output is not debounced. When the PD terminal is asserted high,
the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated
on the RESET terminal so as to force a reset of the TSB41LV01 internal logic.
The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node.
The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 4 and Table 5 in the Application
Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable,
and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input,
regardless of the state of the LCtrl bit).
The LPS input is considered inactive if it remains low for more than 2.6
µs
and is considered active otherwise.
When the TSB41LV01 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state
in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for more than 26
µs,
the PHY-LLC interface is put
into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also
held in the disabled state during hardware reset. The TSB41LV01 continues the necessary repeater functions
required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and return it
to normal operation.
When the PHY-LLC interface in the low-power disabled state, the TSB41LV01 automatically enters a low-power
mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41LV01
disables its internal clock generators and also disables various voltage and current reference circuits depending
on the state of the port (some reference circuitry must remain active in order to detect new cable connections,
disconnections, or incoming TPBias, for example). The lowest power consumption (the
ultralow-power sleep
mode) is attained when the port is either disconnected, or disabled with the port’s interrupt enable bit cleared.
The TSB41LV01 exits the low-power mode when the LPS input is asserted high or when a port event occurs
which requires that the TSB41LV01 become active in order to respond to the event or to notify the LLC of the
event (e.g., incoming bias is detected on a suspended port, a disconnection is detected on a suspended port,
a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the
PHY-LLC interface will be initialized and become operative) within 7.3 ms after LPS is asserted high when the
TSB41LV01 is in the low-power mode.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
TSB41LV01
IEEE 1394A ONE-PORT CABLE
TRANSCEIVER/ARBITER
SLLS365A – AUGUST 1999 – REVISED NOVEMBER 2000
description (continued)
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the
C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would
otherwise cause C/LKON to be active.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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