For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1998
DSC-2747/7
1
IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT72401/IDT72403
IDT72402/IDT72404
NC/OE
(1)
IR
SI
D
0
D
1
D
2
D
3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vcc
SO
OR
Q
0
Q
1
Q
2
Q
3
MR
NC/OE
(2)
IR
SI
D
0
D
1
D
2
D
3
D
4
GND
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
Vcc
SO
OR
Q
0
Q
1
Q
2
Q
3
Q
4
MR
2747 drw 02
2747 drw 03
PLASTIC DIP (P16-1, order code: P)
CERDIP (D16-1, order code: D)
SOIC (SO16-1, order code: SO)
TOP VIEW
NOTES:
1. Pin 1: NC - No Connection IDT72401,
OE
- IDT72403
2. Pin 1: NC - No Connection IDT72402,
OE
- IDT72404
PLASTIC DIP (P18-1, order code: P)
CERDIP (D18-1, order code: D)
SOIC (SO18-1, order code: SO)
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect
to GND
Storage Temp.
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
GND
Parameter
Supply Voltage
Commercial/Military
Supply Voltage
Input High Voltage
Input High Voltage
Operating Temperature
Commercial
Operating Temperature
Military
Min. Typ. Max. Unit
4.5
0
2.0
—
0
–55
5.0
0
—
—
—
—
5.5
0
—
0.8
70
125
V
V
V
V
°C
°C
T
STG
I
OUT
–55 to +125
–50 to +50
–65 to +150
–50 to +50
°C
mA
V
IH
V
IL(1)
T
A
T
A
NOTE:
2747 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2747 tbl 02
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
IDT72401
IDT72402
IDT72403
IDT72404
Commercial
f
IN
= 45,35,25,15,10 MHz
Symbol
I
IL
I
IH
V
OL
V
OH
I
OS
(1)
I
HZ(2)
I
LZ(2)
I
CC(3,4)
Parameter
Low-Level Input Current
High-Level Input Current
Low-Level Output Voltage
High-Level Output Voltage
Output Short-Circuit Current
HIGH Impedance Output Current
LOW Impedance Output Current
Active Supply Current
Test Conditions
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Min., I
OL
= 8mA
V
CC
= Min., I
OH
= -4mA
V
CC
= Max., V
O
= GND
V
CC
= Max., V
O
= 2.4V
V
CC
= Max., V
O
= 0.4V
V
CC
= Max., f = 10MHz
Min.
–10
—
—
2.4
–20
—
–20
—
Max.
—
10
0.4
—
–110
20
—
35
IDT72401
IDT72402
IDT72403
IDT72404
Military
f
IN
= 35,25,15,10 MHz
Min.
–10
—
—
2.4
–20
—
–20
—
Max.
—
10
0.4
—
–110
20
—
45
Unit
µA
µA
V
V
mA
µA
µA
mA
04
NOTES:
2747 tbl
1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.
2. IDT72403 and IDT72404 only.
3. Tested with outputs open (I
OUT
= 0).
OE
is HIGH for IDT72403/72404.
4. For frequencies greater than 10MHz, I
CC
= 35mA + (1.5mA x [f - 10MHz]) commercial, and I
CC
= 45mA + (1.5mA x [f - 10MHz]) military.
2
IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONDITIONS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Commercial
IDT72401L45
IDT72402L45
IDT72403L45
IDT72404L45
Min.
Max.
9
11
0
13
9
11
20
10
3
13
0
—
—
—
—
—
—
—
—
—
—
—
IDT72401L35
IDT72402L35
IDT72403L35
IDT72404L35
Min.
Max.
9
17
0
15
9
17
25
10
3
15
0
—
—
—
—
—
—
—
—
—
—
—
Commercial and Military
IDT72401L25 IDT72401L15
IDT72402L25 IDT72402L15
IDT72403L25 IDT72403L15
IDT72404L25 IDT72404L15
Min.
Max.
Min.
Max.
11
24
0
20
11
24
25
10
5
20
0
—
—
—
—
—
—
—
—
—
—
—
11
25
0
30
11
25
25
25
5
30
0
—
—
—
—
—
—
—
—
—
—
—
IDT72401L10
IDT72402L10
IDT72403L10
IDT72404L10
Min.
Max.
11
30
0
40
11
25
30
35
5
30
0
—
—
—
—
—
—
—
—
—
—
—
Symbol
t
SIH
t
SIL
t
IDS
t
IDH
t
SOH
t
SOL
t
MRW
t
MRS
t
SIR
t
HIR
t
SOR(4)
(1)
(1)
Parameter
Shift in HIGH Time
Shift in LOW TIme
Input Data Set-up
Input Data Hold Time
Shift Out HIGH Time
Shift Out LOW Time
Master Reset Pulse
Master Reset Pulse to SI
Data Set-up to IR
Data Hold from IR
Data Set-up to OR HIGH
Figure
2
2
2
2
5
5
8
8
4
4
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2747 tbl 05
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Commercial
IDT72401L45
IDT72402L45
IDT72403L45
IDT72404L45
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
9
9
45
18
18
45
18
19
—
19
30
25
25
20
12
12
—
—
IDT72401L35
IDT72402L35
IDT72403L35
IDT72404L35
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
9
9
35
18
20
35
18
20
—
20
34
28
28
20
15
12
—
—
Commercial and Military
IDT72401L25 IDT72401L15
IDT72402L25 IDT72402L15
IDT72403L25 IDT72403L15
IDT72404L25 IDT72404L15
Min.
Max.
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
11
11
25
21
28
25
19
34
—
34
40
35
35
25
20
15
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
11
11
15
35
40
15
35
40
—
40
65
35
35
35
30
25
—
—
IDT72401L10
IDT72402L10
IDT72403L10
IDT72404L10
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
11
11
10
40
45
10
40
55
—
55
65
40
40
40
35
30
—
—
Symbol
f
IN
t
IRL(1)
t
IRH
(1)
Parameter
Shift In Rate
Shift In to Input Ready LOW
Shift In to Input Ready HIGH
Shift Out Rate
Shift Out to Output Ready LOW
Shift Out to Output Ready HIGH
Output Data Hold (Previous Word)
Output Data Shift (Next Word)
Data Throughput or "Fall-Through"
Master Reset to OR LOW
Master Reset to IR HIGH
Master Reset to Data Output LOW
Output Valid from
OE
LOW
Output High-Z from
OE
HIGH
Input Ready Pulse HIGH
Output Ready Pulse HIGH
Figure
2
2
2
5
5
5
5
5
4, 7
8
8
8
9
9
4
7
Unit
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
OUT
t
ORL(1)
t
ORH(1)
t
ODH
t
ODS
t
PT
t
MRORL
t
MRIRH
t
MRQ
t
OOE(3)
t
HZOE
t
IPH
(3,4)
(2,4)
t
OPH(2,4)
NOTES:
2747 tbl 06
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between V
CC
and GND with very short lead length is recommended.
2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of
like speed grades.
3. IDT72403 and IDT72404 only.
4. Guaranteed by design but not currently tested.
3
IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ALL INPUT PULSES:
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2747 tbl 07
3.0V
GND
90%
10%
90%
10%
<3ns
<3ns
2747 drw 04
5V
1.1KΩ
OUTPUT
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
7
Unit
pF
pF
2747 tbl 03
560Ω
30pF*
2747 drw 05
or equivalent circuit
Figure 1. AC Test Load
*Including scope and jig
NOTE:
1. Characterized values, not currently tested.
SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT (D
0-3
,
4
)
Data input lines. The IDT72401 and IDT72403 have a 4-bit
data input. The IDT72402 and IDT72404 have a 5-bit data input.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input
data to be written to it. When IR is LOW the FIFO is unavailable
for new input data. IR is also used to cascade many FlFOs
together, as shown in Figures 10 and 11.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q
0-3, 4
) contains
valid data. When OR is LOW, the FIFO is unavailable for new
output data. OR is also used to cascade many FlFOs together,
as shown in Figures 10 and 11.
OUTPUT ENABLE (
OE
) (IDT72403 AND IDT72404 ONLY)
Output enable is used to read FIFO data onto a bus.
OE
is
active LOW.
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When
SI is HIGH, data can be written to the FIFO via the D
0-3, 4
lines.
SHIFT OUT (SO)
Shift Out controls the output of data of the FIFO. When SO
is HIGH, data can be read from the FIFO via the Data Output
(Q
0-3, 4
) lines.
MASTER RESET (
MR
)
Master Reset clears the FIFO of any data stored within.
Upon power up, the FIFO should be cleared with a
MR
.
MR
is active LOW.
OUTPUTS:
DATA OUTPUT (Q
0-3
,
4
)
Data Output lines. The IDT72401 and IDT72403 have a 4-
bit data output. The IDT72402 and IDT72404 have a 5-bit data
output.
4
IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
These 64 x 4 and 64 x 5 FIFOs are designed using a dual
port RAM architecture as opposed to the traditional shift
register approach. This FIFO architecture has a write pointer,
a read pointer and control logic, which allow simultaneous
read and write operations. The write pointer is incremented by
the falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (
OE
) provides the
capability of three-stating the FIFO outputs.
FIFO RESET
The FIFO must be reset upon power up using the Master
Reset (
MR
) signal. This causes the FlFO to enter an empty state,
signified by Output Ready (OR) being LOW and Input Ready (IR)
being HIGH. In this state, the data outputs (Q
0-3, 4
) will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HlGH transition of Shift In (Sl).
This loads input data into the first word location of the FIFO and
causes Input Ready (IR) to go LOW. On the HlGH-to-LOW transi-
tion of SI, the write pointer is moved to the next word position and
IR goes HIGH, indicating the readiness to accept new data. If the
FIFO is full, IR will remain LOW until a word of data is shifted out.
DATA OUTPUT
Data is shifted out on the HlGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be
advanced to the next word location. If data is present, valid
data will appear on the outputs and Output Ready (OR) will
go HIGH. If data is not present, OR will stay LOW indicating
the FIFO is empty. The last valid word read from the FIFO will
remain at the FlFOs output when it is empty. When the FIFO
is not empty, OR goes LOW on the LOW-to-HIGH transition of
SO. Previous data remains on the output until the HIGH-to-
LOW transition of SO).
FALL THROUGH MODE
The FIFO operates in a fall-through mode when data gets
shifted into an empty FIFO. After a fall-through delay the data
propagates to the output. When the data reaches the output,
the Output Ready (OR) goes HIGH. Fall-through mode also
occurs when the FIFO is completely full. When data is shifted
out of the full FIFO, a location is available for new data. After
a fall-through delay, the Input Ready (IR) goes HIGH. If Shift
In (SI) is HIGH, the new data can be written to the FIFO.
Since these FlFOs are based on an internal dual-port RAM
architecture with separate read and write pointers, the fall-
through time (t
PT
) is one cycle long. A word may be written into
the FIFO on a clock cycle and can be accessed on the next
clock cycle.
1/f
IN
t
SIH
SI
t
SIL
1/f
IN
t
IRH
IR
t
IDS
INPUT DATA
2747 drw 06
t
IDH
t
IRL
Figure 2. Input Timing
SI
(7)
(2)
(4)
(1)
IR
(3)
(5)
(6)
INPUT DATA
STABLE DATA
2747 drw 07
NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2. Input Data is loaded into the first word.
3. IR goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
Figure 3. The Mechanism of Shifting Data Into the FIFO
stm32/stm8
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