QP27C256 & QP27C256L
June 18, 2009
QP27C256 – 256 Kilobit (32K x 8) CMOS EPROM
General Description
The QP27C256 is a 32Kx8 (256-Kbit), UV erasable programmable read-only memory. It operates from a single +5 V
supply, has a static standby mode, and features fast single address location programming. The QP27C256 meets the
same specification requirements and utilizes the same programming methodology as the AMD 27C256 that it replaces.
Products are available in windowed and non-windowed (OTP) ceramic hermetic packages.
Data is typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT
states. The device offers separate Output Enable (
OE
) and Chip Enable (
CE
) pins, eliminating bus contention in a
multiple bus system.
Typical power consumption is only 80 mW in active mode, and 100
μW
in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at
random. The device is programmed identically to the AMD27C256 device that it replaces, using the same programming
algorithm (100 us pulses).
The QP27C256 features:
-
Same programming algorithm as the AMD27C256, allowing it to be programmed using the same equipment,
data and algorithm. When programming this device select AMD as the manufacturer and 27C256 as the device
type.
-
Speed options as fast as 55ns
-
JEDEC Pinout
-
Single +5V power supply
-
CMOS and TTL input/output compatibility
-
Two line control functions
-
Programming time typically 4 seconds.
The device/family is constructed using an advanced UV CMOS wafer fabrication process.
Block Diagram
2945 Oakmead Village Ct, Santa Clara, CA 95051
•
Phone:
(408) 737-0992
•
Fax:
(408) 736—8708
•
Internet:
www.qpsemi.com
QP27C256 & QP27C256L
Pin Name
A
0
– A
14
CE ( E )
D
Q0
– D
Q7
OE ( G )
PGM ( P )
V
CC
V
PP
V
ss
NC
Function
Address Inputs
Chip Enable Input
Data Input/Output
Output Enable Input
Program Enable Input
V
CC
Supply Voltage
Program Voltage Input
Ground
No Connection
Connection Diagrams
CERDIP / CERPACK
Device Type
LCC
Functional Description
Device Erasure
In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A
dosage of 15 W seconds/cm
2
is required to completely erase the device. This dosage can be obtained by exposure to
an ultraviolet lamp with a wavelength of 2537Å and an intensity of 12,000
μW/cm
2
for 15 to 20 minutes. The device
should be directly under and about one inch from the source, and all filters should be removed from the UV light source
prior to erasure.
Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000Å, such as
fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any
light source should be prevented for maximum system reliability. Simply cover the package window with an opaque
label or substance.
Device Programming
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Page 2 of 13
QP27C256 & QP27C256L
Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into
the device through the programming procedure.
The device enters the programming mode when 12.75V ± 0.25V is applied to the V
PP
pin, and both
OE
is at V
IH
&
CE
are at V
IL
.
For programming, the data to be programmed is applied 8 bits in parallel to the data pins.
The programming algorithm uses a 100
μs
programming pulse and gives each address only as many pulses as needed
to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process
is repeated while sequencing through each address of the device. This part of the algorithm is done with V
CC
= 6.25 V to
assure that each bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the
entire EPROM memory is verified at V
CC
= V
PP
= 5.25 V.
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for
devices may be common. A TTL low-level program pulse applied to one device’s
and
OE
CE
CE
, all like inputs of the
input with V
PP
= 12.75 V ± 0.25 V
HIGH will program that particular device. A high-level
CE
input inhibits the other devices from being
programmed.
Program Verify
Verification should be performed on the programmed bits to determine that they were correctly programmed. Verify
should be performed with
OE
at V
IL
,
CE
at V
IH
and V
PP
between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0–DQ7. This mode
is primarily intended for programming equipment to automatically match a device to be programmed with its
corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is
required when programming the device. To activate this mode, the programming equipment must force V
H
on address
line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V
IL
to V
IH
(that is, changing the address from 00h to 01h). All other address lines must be held at V
IL
during the autoselect mode.
Byte 0 (A0 = V
IL
) represents the manufacturer code, and Byte 1 (A0 = V
IH
), the device identifier code. Both codes have
odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (
CE
) and Output Enable (
OE
OE
) must be driven low.
CE
controls the
power to the device and is typically used to select the device.
enables the device to output data, independent of
device selection. Addresses must be stable for at least t
ACC
–t
OE
.
Standby Mode
The device enters the CMOS standby mode when
The device enters the TTL-standby mode when
CE
CE
is at V
CC
± 0.3 V. Maximum V
CC
current is reduced to 100
μA.
OE
is at V
IH
. Maximum VCC current is reduced to 1.0 mA. When in
input.
either standby mode, the device places its outputs in a high-impedance state, independent of the
Output OR Connection
To accommodate multiple memory connections, a two-line control function provides:
•
•
CE
Low memory power dissipation
Assurance that output bus contention will not occur.
OE
should be decoded and used as the primary device selecting function, while
be made a common connection
to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low-power standby mode and that the output pins are only active when data is desired from
a particular memory device.
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading
of the device. As a minimum, a 0.1μF ceramic capacitor (high frequency, low inductance) should be used on each
device between V
CC
and V
SS
to minimize transient effects. In addition, to overcome the voltage drop caused by the
inductive effects of the printed circuit board traces on EPROM arrays, a 4.7μF bulk electrolytic capacitor should be used
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Page 3 of 13
QP27C256 & QP27C256L
between V
CC
and V
SS
for each eight devices. The location of the capacitor should be close to where the power supply is
connected to the array.
MODE Select Table
Mode
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
Program Verify
Program Inhibit
Manufacturer Code
Device Code
CE
OE
A
0
X
X
X
X
X
X
X
V
IL
V
IH
A
9
X
X
X
X
X
X
X
V
H
V
H
V
PP
Outputs
X
X
X
X
V
PP
V
PP
V
PP
X
X
D
OUT
High Z
High Z
High Z
D
IN
D
OUT
High Z
01h
10h
Notes
\1
\1
\1
\1
\1
\1
\1
\1 \2 \3 \4
\1 \2 \3 \4
V
IL
X
V
IH
V
CC
±0.3V
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
X
X
V
IH
V
IL
V
IH
V
IL
V
IL
Notes:
\1
X = Either V
IH
or V
IL
\2
V
H
= 12.0V ± 0.5V
\3
A
1
-A
8
& A
10
-A
14
= V
IL
\4
Device Manufacture Code and Device ID match original AMD device for programming compatibility
Absolute Maximum Ratings
Stresses above the AMR may cause permanent damage, extended operation at AMR may degrade performance and affect reliability
Condition
Units
Notes
Power Supply (V
CC
)
-0.6 to +7.0 Volts DC
Voltage with Respect to V
SS
All pins except A
9
, V
PP
, V
CC
-0.6 to V
CC
+0.6 Volts
A
9
and V
PP
-0.6 to 13.5 Volts
Storage Temperature Range
-65 to +150 ºC
Lead Temperature (soldering, 10 seconds)
+300 ºC
Junction Temperature (T
J
)
+150 ºC
Maximum Operating Temperature
Commercial Devices
0 to 70 ºC
Industrial Devices
-40 to 85 ºC
Military Temperature Range
-55 to 125 ºC
Data Retention
10 Years, minimum
Device must not be removed from or inserted into a socket when V
CC
or V
PP
is applied.
\5 \9
\6 \9
\7
\7
\7 \8
\7 \8
\7 \8
Recommended Operating Conditions
Condition
Supply Voltage Range (V
CC
)
Input or Output Voltage Range
Minimum High-Level Input Voltage (V
IH
)
Maximum Low-Level Input Voltage (V
IL
)
Case Operating Range (T
c
)
Commercial Devices
Industrial Devices
Military Temperature Range
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Units
4.5 to 5.5
0.0 to V
CC
2.0
0.8
Volts DC
Volts DC
Volts DC
Volts DC
Notes
\5 \6
0 to 70 ºC
-40 to 85 ºC
-55 to 125 ºC
\7 \8
\7 \8
\7 \8
Page 4 of 13
QP27C256 & QP27C256L
\5 – Minimum DC Input Voltage on input or I/O pins –0.5V. During voltage transitions, the input may overshoot V
SS
to –
2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC+0.5V. During transitions, input
and I/O pins may overshoot to V
CC
+2.0V for periods up to 20ns.
\6 – Minimum DC Input Voltage on A
9
is –0.5V. During voltage transitions, A
9
and V
PP
may overshoot V
SS
to –2.0V for
periods of up to 20ns. A
9
and V
PP
must not exceed +13.5V at any time.
\7 – Do not exceed 125ºC T
C
or T
J
for plastic package devices.
\8 – Maximum PD, Maximum T
J
Are Not to Be Exceeded.
\9 – During transitions, the inputs may undershoot to –2.0 V dc for periods less than 20 ns.
\10 – V
PP
may be connected directly to V
CC
except during programming.
\11 – Qualification Only.
\12 – If not tested, shall be guaranteed to the limits specified.
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test
Symbol
Conditions
-55ºC
≤TA≤+125ºC
Unless Otherwise Specified
Min
Max
Unit
Input Load Current
Output Leakage Current
Operating Current, TTL
I
LI
I
LO
I
CC TTL
All other inputs at either V
CC
or GND
V
IN
= 5.5V or 0.0V
-10.0
-10.0
+10.0
+10.0
85
60
60
60
60
50
60
50
60
50
60
50
60
50
60
50
60
50
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
OIT
= 5.5V or 0.0V
OE
=
CE
= V
IL
35ns
45ns
55ns
70ns
V
PP
= V
CC
O
0
-O
7
= 0 mA
f = 1/t
ACC
max
QP27C256 90ns
QP27C256L 90ns
QP27C256 120ns
QP27C256L 120ns
QP27C256 150ns
QP27C256L 150ns
QP27C256 170ns
QP27C256L 170ns
QP27C256 200ns
QP27C256L 200ns
QP27C256 250ns
QP27C256L 250ns
QP27C256 300ns
QP27C256L 300ns
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Page 5 of 13
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