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IDT71T75602S225BG8: 产品描述ZBT SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, MS-028-AA, BGA-119; 产品类别存储存储; 文件大小474KB，共23页; 制造商IDT (Integrated Device Technology)

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IDT71T75602S225BG8概述

ZBT SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, MS-028-AA, BGA-119

IDT71T75602S225BG8规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	14 X 22 MM, MS-028-AA, BGA-119
针数	119
Reach Compliance Code	not_compliant
ECCN代码	3A991.B.2.A
最长访问时间	3 ns
其他特性	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	225 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B119
JESD-609代码	e0
长度	22 mm
内存密度	18874368 bit
内存集成电路类型	ZBT SRAM
内存宽度	36
湿度敏感等级	3
功能数量	1
端子数量	119
字数	524288 words
字数代码	512000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	512KX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA119,7X17,50
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	225
电源	2.5 V
认证状态	Not Qualified
座面最大高度	2.36 mm
最大待机电流	0.04 A
最小待机电流	2.38 V
最大压摆率	0.315 mA
最大供电电压 (Vsup)	2.625 V
最小供电电压 (Vsup)	2.375 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn63Pb37)
端子形式	BALL
端子节距	1.27 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	20
宽度	14 mm

IDT71T75602S225BG8文档预览

512K x 36, 1M x 18

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

Advance

Information

IDT71T75602

IDT71T75802

Features

512K x 36, 1M x 18 memory configurations

Supports high performance system speed - 166 MHz

(3.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

2.5V power supply (±5%)

2.5V I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

Description

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit

(18 Megabit) synchronous SRAMs. They are designed to eliminate dead

bus cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT

, or Zero

Bus Turnaround.

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be it

read or write.

The IDT71T75602/802 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable

CEN

pin allows operation of the IDT71T75602/802

to be suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

TMS

TDI

TCK

TDO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Input

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

N/A

Synchronous

Static

5313 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

DECEMBER 2001

DSC-5313/04

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Advance Information

Commercial Temperature Range

Description (cont.)

The data bus will tri-state two cycles after the chip is deselected or a write

is initiated.

The IDT71T75602/802 have an on-chip burst counter. In the burst

mode, the IDT71T75602/802 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the

LBO

input pin. The

LBO

pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

The IDT71T75602/802 SRAMs utilize IDT’s latest high-performance

2.5V CMOS process, and are packaged in a JEDEC Standard 14mm x

20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid

array (BGA).

Pin Definitions

(1)

Symbol

-A

ADV/LD

Pin Function

Address Inputs

Advance / Load

I/O

Active

N/A

Description

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,

ADV/LD low,

CEN

low, and true chip enables.

ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is

sampled lo w at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,

any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced

for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.

R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access

to the memory array. The data bus activity for the current cycle takes place two clock cycles later.

Synchronous Clock Enable Input. When

CEN

is sampled high, all other synchronous inputs, including clock are

ignored and outputs remain unchanged. The effect of

CEN

sampled high on the device outputs is as if the low

to high clock transition did not occur. For normal operation,

CEN

must be sampled low at rising edge of clock.

Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles

(when R/W and ADV/LD are sampled low) the appropriate byte write signal (BW

-BW

) must be valid. The byte

write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled

high. The appropriate byte(s) of data are written into the device two cycles later.

-BW

can all be tied low if

always doing write to the entire 36-bit word.

Synchronous active low chip enable.

and

are used with CE

to enable the IDT71T75602/802 (CE

sampled high or CE

sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The

ZBT

has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.

Synchronous active high chip enable. CE

is used with

and

to enable the chip. CE

has inverted polarity

but otherwise identical to

and

This is the clock input to the IDT71T75602/802. Except for

OE,

all timing references for the device are made with

respect to the rising edge of CLK.

Synchronous data input/output (I/O) pins. Both the data input path and data output path are reg istered and triggered

by the rising edge of CLK.

Burst order selection input. When

LBO

is high the Interleaved burst sequence is sele cted. When

LBO

is low the

Linear burst sequence is selected.

LBO

is a static input and it must not change during device operation.

Asynchronous output enable.

must be low to read data from the 71T75602/802. Whe n

is high the I/O pins

are in a high-impedance state.OE does not need to be actively controlled for read and write cycles. In normal

operation,

can be tied low.

Gives input command for TAP controller. Sampled o n rising edge of TDK.

Serial input of registers placed between TDI and TDO. Sampled o n rising edge of TCK.

Clock input of TAP controller. Each TAP event is clocked. Test inp uts are captured on rising edge of TCK, while

test outputs are driven from the falling edge of TCK.

Serial outout of registers placed between TDI and TDO. This outout is active depending on the state of the TAP

controller.

Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its

lowest power consumption level. Data retention is guaranteed in Sleep Mode.

2.5V core power supply.

2.5V I/O Supply.

Ground.

5313 tbl 02

R/W

CEN

Read / Write

Clock Enable

N/A

LOW

-BW

Individual Byte

Write Enables

LOW

Chip Enables

LOW

CLK

I/O

-I/O

I/O

-I/O

LBO

Chip Enable

Clock

Data Input/Output

Linear Burst Order

Output Enable

I/O

HIGH

N/A

LOW

TMS

TDI

TCK

TDO

DDQ

Test Mode Select

Test Data Input

Test Clock

Test Data Output

Sleep Mode

Power Supply

Ground

N/A

HIGH

N/A

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Advance Information

Commercial Temperature Range

Functional Block Diagram

LBO

Address A [0:18]

CE1,

CE2,

CE2

R/W

CEN

ADV/LD

BWx

Clk

Control

512Kx36 BIT

MEMORY ARRAY

Address

Input Register

Control Logic

Mux

Sel

Clk

Clock

Output Register

Gate

5313 drw 01

Data I/O [0:31],

I/O P[1:4]

LBO

Address A [0:19]

CE1,

CE2,

CE2

R/W

CEN

ADV/LD

BWx

Clk

1Mx18 BIT

MEMORY ARRAY

Address

Control

Input Register

Control Logic

Mux

Sel

Clk

Clock

Output Register

Gate

5313 drw 01b

Data I/O [0:15],

I/O P[1:2]

6.42

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Advance Information

Commercial Temperature Range

Recommended DC Operating

Conditions

Symbol

DDQ

Parameter

Core Supply Voltage

I/O Supply Voltage

Ground

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

Min.

2.375

1.7

-0.3

(1)

Typ.

2.5

____

Recommended Operating

Temperature and Supply Voltage

Max.

2.625

Unit

5313 tbl 03

Grade

Commercial

Temperature

(1)

0°C to +70°C

2.5V±5%

DDQ

2.5V±5%

5313 tbl 05

NOTE:

1. T

is the “instant on” case temperature.

+0.3

DDQ

+0.3

0.7

NOTE:

1. V

(min.) = –0.8V for pulse width less than t

CYC

/2, once per cycle.

Pin Configuration 512K x 36

CLK

R/W

CEN

ADV/LD

I/O

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

I/O

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5313 drw 02

I/O

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

I/O

LBO

NC / TMS

(2)

NC / TDI

(2)

NC / TDO

(2)

NC / TCK

(2,3)

Top View

100 TQFP

NOTES:

1. Pins 14, 16, and 66 do not have to be connected directly to V

as long as the input voltage is

≥

2. Pins 38, 39 and 43 will be pulled internally to V

if not actively driven. To disable the TAP controller without

interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to V

or V

and pin

42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected

“NC” and the JTAG circuit will remain disabled from power up.

3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.

6.42

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Advance Information

Commercial Temperature Range

ADV/LD

Pin Configuration 1Mx 18

CLK

R/W

CEN

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

Absolute Maximum Ratings

(1)

Symbol

TERM

(2)

Rating

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Operating Temperature

Temperature Under Bias

Storage Temperature

Power Dissipation

DC Output Current

Commercial

-0.5 to +3.6

-0.5 to V

+0.5

-0.5 to V

DDQ

+0.5

0 to +70

-55 to +125

2.0

Unit

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

5313 drw 02a

TERM

(3,6)

TERM

(4,6)

TERM

(5,6)

(7)

BIAS

STG

OUT

NOTES:

1. Pins 14, 16, and 66 do not have to be connected directly to V

as long as

the input voltage is

≥

2. Pins 38, 39 and 43 will be pulled internally to V

if not actively driven. To

disable the TAP controller without interfering with normal operation, several

settings are possible. Pins 38, 39 and 43 could be tied to V

or V

and

pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)

pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit

will remain disabled from power up.

3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin

TQFP package for the 36M ZBT device.

Top View

100 TQFP

5313 tbl 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V

terminals only.

3. V

DDQ

terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any input or I/O pin cannot exceed V

DDQ

during power

supply ramp up.

7. T

is the “instant on” case temperature.

NC / TDO

(2)

NC / TCK

(2,3)

LBO

NC / TMS

(2)

NC / TDI

(2)

100-Pin TQFP Capacitance

= +25°C, f = 1.0MHz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

5313 tbl 07

165 fBGA Capacitance

= +25°C, f = 1.0MHz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

TDB

Unit

5313 tbl 07b

119 BGA Capacitance

= +25°C, f = 1.0MHz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

5313 tbl 07a

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

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IDT71T75602S225BG8

IDT71T75602S225BG8概述

IDT71T75602S225BG8规格参数

IDT71T75602S225BG8文档预览

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