TRANSISTOR 2900 mA, 20 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, HALOGEN FREE AND ROHS COMPLIANT, SC-70, 6 PIN, FET General Purpose Small Signal
SI1410EDH-T1-GE3规格参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Vishay(威世)
零件包装代码
SC-70
包装说明
SMALL OUTLINE, R-PDSO-G6
针数
6
Reach Compliance Code
unknown
ECCN代码
EAR99
配置
SINGLE WITH BUILT-IN DIODE AND RESISTOR
最小漏源击穿电压
20 V
最大漏极电流 (Abs) (ID)
2.9 A
最大漏极电流 (ID)
2.9 A
最大漏源导通电阻
0.07 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JESD-30 代码
R-PDSO-G6
JESD-609代码
e3
湿度敏感等级
1
元件数量
1
端子数量
6
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度（摄氏度）
260
极性/信道类型
N-CHANNEL
最大功率耗散 (Abs)
1.56 W
认证状态
Not Qualified
表面贴装
YES
端子面层
PURE MATTE TIN
端子形式
GULL WING
端子位置
DUAL
处于峰值回流温度下的最长时间
30
晶体管应用
SWITCHING
晶体管元件材料
SILICON
SI1410EDH-T1-GE3文档预览
Si1410EDH
Vishay Siliconix
N-Channel 20 V (D-S) MOSFET
PRODUCT SUMMARY
V
DS
(V)
20
R
DS(on)
(Ω)
0.070 at V
GS
= 4.5 V
0.080 at V
GS
= 2.5 V
0.100 at V
GS
= 1.8 V
I
D
(A)
3.7
3.4
3.0
FEATURES
•
Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET
®
Power MOSFETs: 1.8 V Rated
• ESD Protected: 2000 V
• Thermally Enhanced SC-70 Package
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
SOT-363
SC-70 (6-LEADS)
D
1
6
D
Marking Code
AA
D
2
5
D
XX
YY
1 kΩ
Lot Traceability
and Date Code
Part # Code
G
• Load Switching
• PA Switch
• Level Switch
D
G
3
4
S
Top
View
S
Ordering Information:
Si1410EDH-T1-E3 (Lead (Pb)-free)
Si1410EDH-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (T
J
= 150 °C)
a
Pulsed Drain Current
Continuous Diode Current (Diode Conduction)
a
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
T
A
= 25 °C
T
A
= 85 °C
T
A
= 25 °C
T
A
= 85 °C
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
stg
1.4
1.56
0.81
- 55 to 150
3.7
2.6
8
0.9
1.0
0.52
W
°C
5s
20
± 12
2.9
2.0
A
Steady State
Unit
V
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
a
Maximum Junction-to-Foot (Drain)
Notes:
a. Surface mounted on 1" x 1" FR4 board.
t
≤
5s
Steady State
Steady State
Symbol
R
thJA
R
thJF
Typical
60
100
34
Maximum
80
125
45
°C/W
Unit
Document Number: 71409
S10-0935-Rev. B, 19-Apr-10
www.vishay.com
1
Si1410EDH
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
Diode Forward Voltage
a
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 10 V, R
L
= 10
Ω
I
D
≅
1 A, V
GEN
= 4.5 V, R
g
= 6
Ω
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 3.7 A
5.6
0.75
1.10
0.15
0.4
1.9
1.2
0.25
0.6
2.8
1.8
µs
8
nC
a
Symbol
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(on)
g
fs
V
SD
Test Conditions
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= 0 V, V
GS
= ± 4.5 V
V
DS
= 0 V, V
GS
= ± 12 V
V
DS
= 16 V, V
GS
= 0 V
V
DS
= 16 V, V
GS
= 0 V, T
J
= 85 °C
V
DS
= 5 V, V
GS
= 4.5 V
V
GS
= 4.5 V, I
D
= 3.7 A
V
GS
= 2.5 V, I
D
= 3.4 A
V
GS
= 1.8 V, I
D
= 1.7 A
V
DS
= 10 V, I
D
= 3.7 A
I
S
= 1.4 A, V
GS
= 0 V
Min.
0.45
Typ.
Max.
Unit
V
±1
± 10
1
5
4
0.055
0.065
0.080
10
0.75
1.1
0.070
0.080
0.100
µA
mA
µA
A
Ω
S
V
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
FPGA/CPLD
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