Micron Confidential and Proprietary
Advance
‡
512Mb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H32M16LF – 8 Meg x 16 x 4 Banks
MT46H16M32LF – 4 Meg x 32 x 4 Banks
MT46H16M32LG – 4 Meg x 32 x 4 Banks
Features
•
V
DD
/V
DDQ
= 1.70–1.95V
•
Bidirectional data strobe per byte of data (DQS)
•
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
•
Differential clock inputs (CK and CK#)
•
Commands entered on each positive CK edge
•
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
•
4 internal banks for concurrent operation
•
Data masks (DM) for masking write data; one mask
per byte
•
Programmable burst lengths (BL): 2, 4, 8, or 16
•
Concurrent auto precharge option is supported
•
Auto refresh and self refresh modes
•
1.8V LVCMOS-compatible inputs
•
Temperature-compensated self refresh (TCSR)
•
Partial-array self refresh (PASR)
•
Deep power-down (DPD)
•
Status read register (SRR)
•
Selectable output drive strength (DS)
•
Clock stop capability
•
64ms refresh
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
-5
-54
-6
-75
Clock Rate
200 MHz
185 MHz
166 MHz
133 MHz
Access Time
5.0ns
5.0ns
5.0ns
6.0ns
Options
•
V
DD
/V
DDQ
–
1.8V/1.8V
•
Configuration
–
32 Meg x 16 (8 Meg x 16 x 4 banks)
–
16 Meg x 32 (4 Meg x 32 x 4 banks)
•
Addressing
–
JEDEC-standard addressing
–
Reduced page size
•
Plastic "green" package
–
60-ball VFBGA (8mm x 9mm)
1
–
90-ball VFBGA (8mm x 13mm)
2
•
Timing – cycle time
–
5ns @ CL = 3 (200 MHz)
–
5.4ns @ CL = 3 (185 MHz)
–
6ns @ CL = 3 (166 MHz)
–
7.5ns @ CL = 3 (133 MHz)
•
Power
–
Standard I
DD2
/I
DD6
–
Low-power I
DD2
/I
DD6
•
Operating temperature range
–
Commercial (0˚ to +70˚C)
–
Industrial (–40˚C to +85˚C)
–
Automotive (–40˚C to +105˚C)
•
Design revision
Notes:
Marking
H
32M16
16M32
LF
LG
BF
B5
-5
-54
-6
-75
None
L
None
IT
AT
:C
1. Only available for x16 configuration.
2. Only available for x32 configuration.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
1
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Features
Table 2: Configuration Addressing
Architecture
Configuration
Refresh count
Row addressing
Column addressing
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K A[12:0]
1K A[9:0]
16 Meg x 32
4 Meg x 32 x 4 banks
8K
8K A[12:0]
512 A[8:0]
Reduced Page Size
16 Meg x 32
4 Meg x 32 x 4 banks
8K
16K A[13:0]
256 A[7:0]
Figure 1: 512Mb Mobile LPDDR Part Numbering
MT 46
Micron Technology
Product Family
46 = Mobile LPDDR
H
32M16 LF BF -6
IT
:C
Design Revision
:C = Third generation
Operating Temperature
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
AT = Automotive (–40°C to +105°C)
Operating Voltage
H = 1.8/1.8V
Power
Configuration
32 Meg x 16
16 Meg x 32
Blank = Standard I
DD2
/I
DD6
L = Low-power I
DD2
/I
DD6
Cycle Time (CL = 3)
Addressing
LF = JEDEC-standard
LG = Reduced page size
-5 = 5ns
t
CK
-54 = 5.4ns
t
CK
-6 = 6ns
t
CK
-75 = 7.5ns
t
CK
Package Codes
BF = 60-ball (8mm x 9mm) VFBGA, “green”
B5 = 90-ball (8mm x 13mm) VFBGA, “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
General Description ......................................................................................................................................... 7
Functional Block Diagrams ............................................................................................................................... 8
Ball Assignments ............................................................................................................................................ 10
Ball Descriptions ............................................................................................................................................ 12
Package Dimensions ...................................................................................................................................... 14
Electrical Specifications .................................................................................................................................. 16
Electrical Specifications – I
DD
Parameters ........................................................................................................ 19
Electrical Specifications – AC Operating Conditions ......................................................................................... 25
Output Drive Characteristics ........................................................................................................................... 30
Functional Description ................................................................................................................................... 33
Commands .................................................................................................................................................... 34
DESELECT ................................................................................................................................................ 35
NO OPERATION ........................................................................................................................................ 35
LOAD MODE REGISTER ............................................................................................................................ 35
ACTIVE ..................................................................................................................................................... 35
READ ........................................................................................................................................................ 36
WRITE ...................................................................................................................................................... 37
PRECHARGE ............................................................................................................................................. 38
BURST TERMINATE .................................................................................................................................. 39
AUTO REFRESH ........................................................................................................................................ 39
SELF REFRESH ........................................................................................................................................... 40
DEEP POWER-DOWN ................................................................................................................................ 40
Truth Tables ................................................................................................................................................... 41
State Diagram ................................................................................................................................................ 46
Initialization .................................................................................................................................................. 47
Standard Mode Register .................................................................................................................................. 50
Burst Length .............................................................................................................................................. 50
Burst Type ................................................................................................................................................. 51
CAS Latency .............................................................................................................................................. 52
Operating Mode ......................................................................................................................................... 53
Extended Mode Register ................................................................................................................................. 54
Temperature-Compensated Self Refresh .................................................................................................... 54
Partial-Array Self Refresh ........................................................................................................................... 55
Output Drive Strength ................................................................................................................................ 55
Status Read Register ....................................................................................................................................... 56
Bank/Row Activation ...................................................................................................................................... 58
READ Operation ............................................................................................................................................. 59
WRITE Operation ........................................................................................................................................... 70
PRECHARGE Operation .................................................................................................................................. 82
Auto Precharge ............................................................................................................................................... 82
Concurrent Auto Precharge ........................................................................................................................ 83
AUTO REFRESH Operation ............................................................................................................................. 88
SELF REFRESH Operation .............................................................................................................................. 89
Power-Down .................................................................................................................................................. 90
Deep Power-Down .................................................................................................................................... 92
Clock Change Frequency ................................................................................................................................ 94
Revision History ............................................................................................................................................. 95
Rev. B – 02/10 ............................................................................................................................................. 95
Rev. A – 01/10 ............................................................................................................................................. 95
Contents
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Table 1: Key Timing Parameters (CL = 3) .......................................................................................................... 1
Table 2: Configuration Addressing .................................................................................................................. 2
Table 3: Ball Descriptions .............................................................................................................................. 12
Table 4: Absolute Maximum Ratings .............................................................................................................. 16
Table 5: AC/DC Electrical Characteristics and Operating Conditions ............................................................... 16
Table 6: Capacitance (x16, x32) ...................................................................................................................... 18
Table 7: I
DD
Specifications and Conditions, –40°C to +85°C (x16) ..................................................................... 19
Table 8: I
DD
Specifications and Conditions, –40°C to +85°C (x32) ..................................................................... 20
Table 9: I
DD
Specifications and Conditions, –40°C to +105°C (x16) ................................................................... 21
Table 10: I
DD
Specifications and Conditions, –40°C to +105°C (x32) ................................................................. 22
Table 11: I
DD6
Specifications and Conditions .................................................................................................. 23
Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 25
Table 13: Target Output Drive Characteristics (Full Strength) .......................................................................... 30
Table 14: Target Output Drive Characteristics (Three-Quarter Strength) .......................................................... 31
Table 15: Target Output Drive Characteristics (One-Half Strength) ................................................................. 32
Table 16: Truth Table – Commands ............................................................................................................... 34
Table 17: DM Operation Truth Table ............................................................................................................. 35
Table 18: Truth Table – Current State Bank
n
– Command to Bank
n
............................................................... 41
Table 19: Truth Table – Current State Bank
n
– Command to Bank
m
.............................................................. 42
Table 20: Truth Table – CKE .......................................................................................................................... 45
Table 21: Burst Definition Table .................................................................................................................... 51
List of Tables
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Figure 1: 512Mb Mobile LPDDR Part Numbering ............................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 8
Figure 3: Functional Block Diagram (x32) ......................................................................................................... 9
Figure 4: 60-Ball VFBGA – Top View, x16 only ................................................................................................. 10
Figure 5: 90-Ball VFBGA – Top View, x32 only ................................................................................................. 11
Figure 6: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 14
Figure 7: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................ 15
Figure 8: Typical Self Refresh Current vs. Temperature – TBD ......................................................................... 24
Figure 9: ACTIVE Command .......................................................................................................................... 36
Figure 10: READ Command ........................................................................................................................... 37
Figure 11: WRITE Command ......................................................................................................................... 38
Figure 12: PRECHARGE Command ................................................................................................................ 39
Figure 13: DEEP POWER-DOWN Command .................................................................................................. 40
Figure 14: Simplified State Diagram ............................................................................................................... 46
Figure 15: Initialize and Load Mode Registers ................................................................................................. 48
Figure 16: Alternate Initialization with CKE LOW ............................................................................................ 49
Figure 17: Standard Mode Register Definition ................................................................................................ 50
Figure 18: CAS Latency .................................................................................................................................. 53
Figure 19: Extended Mode Register ................................................................................................................ 54
Figure 20: Status Read Register Timing .......................................................................................................... 56
Figure 21: Status Register Definition .............................................................................................................. 57
Figure 22: READ Burst ................................................................................................................................... 60
Figure 23: Consecutive READ Bursts .............................................................................................................. 61
Figure 24: Nonconsecutive READ Bursts ........................................................................................................ 62
Figure 25: Random Read Accesses ................................................................................................................. 63
Figure 26: Terminating a READ Burst ............................................................................................................. 64
Figure 27: READ-to-WRITE ............................................................................................................................ 65
Figure 28: READ-to-PRECHARGE .................................................................................................................. 66
Figure 29: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x16) ................................................... 67
Figure 30: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x32) ................................................... 68
Figure 31: Data Output Timing –
t
AC and
t
DQSCK .......................................................................................... 69
Figure 32: Data Input Timing ......................................................................................................................... 71
Figure 33: Write – DM Operation ................................................................................................................... 72
Figure 34: WRITE Burst ................................................................................................................................. 73
Figure 35: Consecutive WRITE-to-WRITE ....................................................................................................... 74
Figure 36: Nonconsecutive WRITE-to-WRITE ................................................................................................. 74
Figure 37: Random WRITE Cycles .................................................................................................................. 75
Figure 38: WRITE-to-READ – Uninterrupting ................................................................................................. 76
Figure 39: WRITE-to-READ – Interrupting ...................................................................................................... 77
Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 78
Figure 41: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 79
Figure 42: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 80
Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 81
Figure 44: Bank Read – With Auto Precharge .................................................................................................. 84
Figure 45: Bank Read – Without Auto Precharge ............................................................................................. 85
Figure 46: Bank Write – With Auto Precharge .................................................................................................. 86
Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 87
Figure 48: Auto Refresh Mode ........................................................................................................................ 88
Figure 49: Self Refresh Mode ......................................................................................................................... 90
Figure 50: Power-Down Entry (in Active or Precharge Mode) .......................................................................... 91
List of Figures
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
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