Component Recognition Program File Number: E207481
Rated 2500V
RMS
for 1 minute
Soldering Profile
Per JEDEC J-STD-020C, MSL=2
2
IL711/IL712/IL721
IL711 Pin Connections
1
2
3
4
5
6
7
8
V
DD1
IN
1
IN
2
GND
1
GND
2
OUT
2
OUT
1
V
DD2
Supply voltage
Data in, channel 1
Data in, channel 2
Ground return for V
DD1
Ground return for V
DD2
Data out, channel 2
Data out, channel 1
Supply voltage
V
DD1
1
8
V
DD2
7
OUT
1
6
OUT
2
5
GND
2
IN
1
2
IN
2
3
GND
1
4
IL711
IL712 Pin Connections
1
2
3
4
5
6
7
8
V
DD1
IN
1
OUT
2
GND
1
GND
2
IN
2
OUT
1
V
DD2
Supply voltage
Data in, channel 1
Data out, channel 2
Ground return for V
DD1
Ground return for V
DD2
Data in, channel 2
Data out, channel 1
Supply voltage
V
DD1
IN
1
OUT
2
GND
1
V
DD2
OUT
1
IN
2
GND
2
IL712
IL721 Pin Connections
1
2
3
4
5
6
7
8
V
DD1
OUT
1
IN
2
GND
1
GND
2
OUT
2
IN
1
V
DD2
Supply voltage
Data out, channel 1
Data in, channel 2
Ground return for V
DD1
Ground return for V
DD2
Data out, channel 2
Data in, channel 1
Supply voltage
V
DD1
OUT
1
IN
2
GND
1
V
DD2
IN
1
OUT
2
GND
2
IL721
Timing Diagram
Legend
t
PLH
t
PHL
t
PW
t
R
t
F
Propagation Delay, Low to High
Propagation Delay, High to Low
Minimum Pulse Width
Rise Time
Fall Time
3
IL711/IL712/IL721
3.3 Volt Electrical Specifications
Electrical specifications are T
min
to T
max
unless otherwise stated.
Parameters
Symbol
Min.
Typ.
Max.
DC Specifications
Input Quiescent Supply Current
IL711
8
10
I
DD1
IL712/IL721
1.5
2
Output Quiescent Supply Current
IL711
3.3
4
I
DD2
IL712/IL721
1.5
2
Logic Input Current
I
I
−10
10
V
DD
– 0.1
V
DD
Logic High Output Voltage
V
OH
0.9 x V
DD
0.8 x V
DD
0
0.1
Logic Low Output Voltage
V
OL
0.5
0.8
Switching Specifications
Maximum Data Rate
IL711/IL712/IL721
100
110
IL711S/IL712S
100
110
IL711T/IL712T/IL721T
130
140
(7)
Pulse Width
PW
10
7.5
Propagation Delay Input to Output
t
PHL
12
18
(High to Low)
Propagation Delay Input to Output
12
18
t
PLH
(Low to High)
Pulse Width Distortion
(2)
2
3
IL711/IL712/IL721
2
3
IL711S/IL712S
PWD
1
3
IL711T/IL712T/IL721T
(3)
Propagation Delay Skew
t
PSK
4
6
Output Rise Time (10%–90%)
t
R
2
4
Output Fall Time (10%–90%)
t
F
2
4
Common Mode Transient Immunity
|CM
H
|,|CM
L
|
20
30
(Output Logic High or Logic Low)
(4)
Channel-to-Channel Skew
t
CSK
2
3
(6)
Dynamic Power Consumption
140
240
Magnetic Field Immunity
(8)
(V
DD2
= 3V, 3V<V
DD1
<5.5V)
Power Frequency Magnetic Immunity
H
PF
1000
1500
Pulse Magnetic Field Immunity
H
PM
1800
2000
Damped Oscillatory Magnetic Field
H
OSC
1800
2000
Cross-axis Immunity Multiplier
(9)
K
X
2.5
Units
μA
mA
mA
mA
μA
V
V
Test Conditions
I
O
=
−20 μA,
V
I
= V
IH
I
O
=
−4
mA, V
I
= V
IH
I
O
= 20
μA,
V
I
= V
IL
I
O
= 4 mA, V
I
= V
IL
Mbps
Mbps
Mbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
kV/μs
ns
μA/MHz
A/m
A/m
A/m
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
50% Points, V
O
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
V
CM
= 300 V
C
L
= 15 pF
per channel
50Hz/60Hz
t
p
= 8µs
0.1Hz – 1MHz
4
IL711/IL712/IL721
5 Volt Electrical Specifications
Electrical specifications are T
min
to T
max
unless otherwise stated.
Parameters
Symbol
Min.
Typ.
Max.
DC Specifications
Input Quiescent Supply Current
IL711
10
15
I
DD1
IL712/IL721
2.5
3
Output Quiescent Supply Current
IL711
5
6
I
DD2
IL712/IL721
2.5
3
Logic Input Current
I
I
−10
10
V
DD
−
0.1
V
DD
Logic High Output Voltage
V
OH
0.9 x V
DD
0.8 x V
DD
0
0.1
Logic Low Output Voltage
V
OL
0.5
0.8
Switching Specifications
Maximum Data Rate
IL711/IL712/IL721
100
110
IL711S/IL712S
100
110
IL711T/IL712T/IL721T
130
150
(7)
Pulse Width
PW
10
7.5
Propagation Delay Input to Output
t
PHL
10
15
(High to Low)
Propagation Delay Input to Output
10
15
t
PLH
(Low to High)
Pulse Width Distortion
(2)
IL711/IL712/IL721
2
3
IL711S/IL712S
PWD
2
3
IL711T/IL712T/IL721T
0.3
3
(10)
Pulse Jitter
t
J
100
Propagation Delay Skew
(3)
t
PSK
4
6
Output Rise Time (10%–90%)
t
R
1
3
Output Fall Time (10%–90%)
t
F
1
3
Common Mode Transient Immunity
20
30
|CM
H
|,|CM
L
|
(Output Logic High or Logic Low)
(4)
Channel to Channel Skew
t
CSK
2
3
(6)
Dynamic Power Consumption
200
340
(8)
Magnetic Field Immunity (V
DD2
= 5V, 3V<V
DD1
<5.5V)
Power Frequency Magnetic Immunity
H
PF
2800
3500
Pulse Magnetic Field Immunity
H
PM
4000
4500
Damped Oscillatory Magnetic Field
H
OSC
4000
4500
(9)
Cross-axis Immunity Multiplier
K
X
2.5
Units
μA
mA
mA
mA
μA
V
V
Test Conditions
I
O
=
−20 μA,
V
I
= V
IH
I
O
=
−4
mA, V
I
= V
IH
I
O
= 20
μA,
V
I
= V
IL
I
O
= 4 mA, V
I
= V
IL
Mbps
Mbps
Mbps
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
kV/μs
ns
μA/MHz
A/m
A/m
A/m
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
50% Points, V
O
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
V
cm
= 300 V
C
L
= 15 pF
per channel
50Hz/60Hz
t
p
= 8µs
0.1Hz – 1MHz
Notes
(apply to both 3.3 V and 5 V specifications):
Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.
2. PWD is defined as |t
PHL
−
t
PLH
|. %PWD is equal to PWD divided by pulse width.
3. t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
between devices at 25°C.
4. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD
2
. CM
L
is the maximum
common mode input voltage that can be sustained while maintaining V
O
< 0.8 V. The common mode voltage slew rates apply to both rising
and falling common mode voltage edges.
5. Device is considered a two terminal device: pins 1–4 shorted and pins 5–8 shorted.
6. Dynamic power consumption is calculated per channel and is supplied by the channel’s input side power supply.
7. Minimum pulse width is the minimum value at which specified PWD is guaranteed.
8. The relevant test and measurement methods are given in the Electromagnetic Compatibility section on p. 6.
9. External magnetic field immunity is improved by this factor if the field direction is “end-to-end” rather than to “pin-to-pin” (see diagram on p. 6).
10. 64k-bit pseudo-random binary signal (PRBS) NRZ bit pattern with no more than five consecutive 1s or 0s; 800 ps transition time.
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