59C11
1K 5.0V CMOS Serial EEPROM
FEATURES
• Low power CMOS technology
• Pin selectable memory organization
- 128 x 8 or 64 x 16 bit organization
• Single 5 volt only operation
• Self timed WRITE, ERAL and WRAL cycles
• Automatic erase before WRITE
• RDY/BSY status information during WRITE
• Power on/off data protection circuitry
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data Retention > 200 Years
• 8-pin DIP or SOIC package
• Available for extended temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
- Automotive: -40˚C to +125˚C
PACKAGE TYPE
DIP
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
RDY/BSY
ORG
V
SS
59C11
SOIC
1
2
3
4
8
7
6
5
CS
CLK
V
CC
RDY/BSY
ORG
V
SS
DESCRIPTION
DI
59C11
The Microchip Technology Inc. 59C11 is a 1K bit Elec-
trically Erasable PROM. The device is configured as
128 x 8 or 64 x 16, selectable externally by means of
the control pin ORG. Advanced CMOS technology
makes this device ideal for low power nonvolatile mem-
ory applications. The 59C11 is available in the stan-
dard 8-pin DIP and a surface mount SOIC package.
DO
BLOCK DIAGRAM
V
CC
V
SS
ORG
MEMORY
ARRAY
128 x 8 or
64 x 16
ADDRESS
DECODER
DATA REGISTER
DI
MODE
DECODE
LOGIC
OUTPUT
BUFFER
DO
CS
RDY/BSY
CLK
CLOCK
GENERATOR
©
1995 Microchip Technology Inc.
DS20040I-page 1
59C11
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
CS
CLK
DI
DO
V
SS
ORG
RDY/BSY
V
CC
PIN FUNCTION TABLE
Function
Chip Select
Serial Clock
Data In
Data Out
Ground
Memory Array Organization
Ready/Busy Status
+5V Power SUpply
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
.....-0.6V to V
CC
+1.0V
Storage temperature
........................-65˚C to +150˚C
Ambient temperature with
power applied......................................-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins..................................... 4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Commercial:
Industrial:
Automotive:
Symbol
V
TH
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
write
I
CCS
Min
2.8
2.0
-0.3
2.4
—
—
—
—
—
—
Max
4.5
Vcc+1
0.8
—
0.4
10
10
7
4
100
Units
V
V
V
V
V
µ
A
µ
A
pF
mA
µ
A
I
OH
= -400
µ
A
I
OL
= 3.2 mA
V
IN
= 0V to V
CC
(Note 1)
V
OUT
= 0V to V
CC
(Note 1)
V
IN
/V
OUT
= 0V (Note 2)
Tamb = 25
°
C, f = 1 MHz
F
CLK
= 1 MHz, V
CC
= 5.5V
CS = 0V, V
CC
= 5.5V
Tamb
Tamb
Tamb
= 0
°
C to 70
°
C
= -40
°
C to +85
°
C
= -40
°
C to 125
°
C
Conditions
V
CC
= +5V (
±
10%)
Parameter
V
CC
detector threshold
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current (all modes)
Standby current
Note 1: Internal resister pull-up at Pin 6. Active output at Pin 7.
Note 2: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
T
CKH
T
CKL
T
CSH
V
IH
CLK
T
DIH
T
DIS
DI
VALID
T
DIH
T
DIS
V
IH
VALID
V
IL
T
CSL
CS
T
CSS
T
PD
VALID
V
IH
V
IL
T
PD
DO
T
CZ
VALID
HIGH
Z
V
IH/
V
OH
V
IL/
V
OL
V
IL
DS20040I-page 2
©
1995 Microchip Technology Inc.
59C11
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time (from CS = low)
Data output disable time (from last clock)
RDY/BSY delay time
Program cycle time (Auto Erase and Write)
Symbol
F
CLK
T
CKH
T
CKL
T
CSS
T
CSH
T
CS
T
DIS
T
DIH
T
PD
T
CZ
T
DDZ
T
RBD
Twc
500
500
50
0
100
100
100
—
0
0
—
—
Min
Max
1
—
—
—
—
—
—
—
400
100
400
400
1
15
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
for 8-bit mode
for ERAL and WRAL
in 8/16-bit modes
CL = 100 pF
CL = 100 pF
CL = 100 pF
Conditions
2.0
2.1
PIN DESCRIPTION
Chip Select (CS)
CLK cycles are not required during the self-timed
WRITE (i.e., auto erase/write) cycle.
After detection of a START condition the specified
number of clock cycles (respectively LOW to HIGH
transitions of CLK) must be provided. These clock
cycles are required to clock in all required opcode,
address, and data bits before an instruction is executed
(see instruction set truth table). When that limit has
been reached, CLK and DI become “Don't Care” inputs
until CS is brought LOW for at least chip select low time
(T
CSL
) and brought HIGH again and a WRITE cycle (if
any) is completed.
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a WRITE cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a WRITE cycle,
the device will go into standby mode as soon as the
WRITE cycle is completed.
CS must be LOW for 100 ns (T
CSL
) minimum between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
2.3
Data In (DI)
2.2
Serial Clock (CLK)
Data In is used to clock in START bit, opcode, address
and data synchronously with the CLK input.
The Serial Clock is used to synchronize the communi-
cation between a master device and the 59C11.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime (with respect to clock high time (T
CKH
) and
clock low time (T
CKL
)). This gives freedom in preparing
opcode, address and data for the controlling master.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but a START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
2.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (T
PD
after the positive
edge of CLK). This output is in HIGH–Z mode except
if data is clocked out as a result of a READ instruction.
DI and DO can be connected together to perform a 3-
wire interface (CS, CLK, DI/DO).
Care must be taken with the leading dummy zero which
is output after a READ command has been detected.
Also, the controlling device must not drive the DI/DO
bus during WRITE cycles.
©
1995 Microchip Technology Inc.
DS20040I-page 3
59C11
2.5
Organization (ORG)
3.0
DATA PROTECTION
This input selects the memory array organization.
When the ORG pin is connected to +5 V the 64 x 16
organization is selected. When it is connected to
ground, the 128 x 8 organization is selected. If the
ORG pin is left unconnected, then an internal pull-up
device will select the 64 x 16 organization. In applica-
tions subject to electrical noise, it is recommended that
this pin not be left floating, but tied either high or low.
During power-up, all modes of operation are inhibited
until V
CC
has reached a level of 2.8 V. During power-
down, the source data protection circuitry acts to inhibit
all modes when V
CC
has fallen below 2.8 V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, EWEN instruction must be
performed before any WRITE, ERAL or WRAL instruc-
tion can be executed. After programming is completed,
the EWDS instruction offers added protection against
unintended data changes.
2.6
Ready/Busy (RDY/BSY)
Pin 7 provides RDY/BSY status information. RDY/BSY
is low if the device is performing a WRITE, ERAL, or
WRAL operation. When it is HIGH the internal, self-
timed WRITE, ERAL or WRAL operation has been
completed and the device is ready to receive a new
instruction.
TABLE 3-1:
INSTRUCTION SET
6 X 16 MODE, ORG = 1
Instruction
READ
WRITE
EWEN
EWDS
ERAL
WRAL
Start Bit
1
1
1
1
1
1
Opcode
1 0 X X
X 1 X X
0 0 1 1
0 0 0 0
0 0 1 0
0 0 0 1
Address
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Data In
—
D15-D0
—
—
—
D15-D0
Data Out
D15-D0
High-Z
High-Z
High-Z
High-Z
High-Z
Number of
Req. CLK CYcles
27
27
11
11
11
27
128 X 8 MODE, ORG = 0
Instruction
READ
WRITE
EWEN
EWDS
ERAL
WRAL
Start Bit
1
1
1
1
1
1
Opcode
1 0 X X
X 1 X X
0 0 1 1
0 0 0 0
0 0 1 0
0 0 0 1
Address
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Data In
—
D7-D0
—
—
—
D7-D0
Data Out
D7-D0
High-Z
High-Z
High-Z
High-Z
High-Z
Number of
Req. CLK CYcles
20
20
12
12
12
20
4.0
4.1
FUNCTIONAL DESCRIPTION
START Condition
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e. clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
Note:
CS must go LOW between consecutive
instructions.
The START bit is detected by the device if CS and DI
are both High with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition) without resulting in any device oper-
ation (READ, WRITE, EWEN, EWDS, ERAL, and
WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
4.2
DI/DO Pins
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
DS20040I-page 4
©
1995 Microchip Technology Inc.
59C11
that precedes the READ operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
the last address bit (A0). Therefore, care must be
taken if DI and DO are connected together as a bus
contention will occur for one clock cycle if A0 is a one.
DO will go into HIGH-Z mode with the positive edge of
the next CLK cycle. This follows the output of the last
data bit D0 or the negative edge of CS, whichever
occurs first. D0 remains stable between CLK cycles for
an unlimited time as long as CS stays HIGH.
The most significant data bit (D15 or D7) is always out-
put first, followed by the lower significant bits (D14 - D0
or D6 - D0).
4.3
READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
bit (logical 0) precedes the 8- or 16-bit output string.
The output data changes during the high state of the
system clock (CLK). The dummy bit is output T
PD
after
the positive edge of CLK, which was used to clock in
FIGURE 4-1:
CLK
READ MODE
CS
SB
DI
1
DO
NOTE:
ORGANIZATION
128 x 8
64 x 16
AN
A6
A5
DN
D7
D15
1
0
X
X
X
T
PD
HIGH - Z
0
DN
D0
X
OPCODE
AN
A0
T
CSL
T
DDZ
NEW INSTRUCTION
OR STANDBY (CS = 0)
4.4
WRITE
The WRITE instruction is followed by 8 or 16 bits of
data which are written into the specified address. The
most significant data bit (D15 or D7) has to be clocked
in first followed by the lower significant data bits (D14 –
D0 or D6 – D0). If a WRITE instruction is recognized
by the device and all data bits have been clocked in,
the device performs an automatic erase cycle on the
specified address before the data are written. The
WRITE cycle is completely self timed and commences
automatically after the rising edge of the CLK signal for
the last data bit (D0).
The WRITE cycle takes 1 ms maximum for 8-bit mode
and 2 ms maximum for 16-bit mode.
FIGURE 4-2:
CLK
WRITE MODE
T
CSL
CS
SB
DI
1
DO
RDY/BSY
X
1
X
HIGH - Z
T
RBD
X
X
X
X
X
OPCODE
AN
A0
DN
D0
NOTE:
ORGANIZATION
128 x 8
64 x 16
AN
A6
A5
DN
D7
D15
T
WC
NEW INSTRUCTION
OR STANDBY (CS = 0)
©
1995 Microchip Technology Inc.
DS20040I-page 5
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