REI Datasheet
SN54LS490, SN74LS490
Dual 4-Bit Decade Counters
Each of these monolithic circuits contains eight master-slave flip-flops and additional gating to
implement two individual 4-bit decade counters in a single package. Each decade counter has
individual clock (1CLK, 2CLK), clear (1CLR, 2CLR), and set-to-9 (1SET9, 2SET9) inputs. BCD count
sequences of any length up to divide-by-100 can be implemented with a single ‘LS490 device. Buffering
on each output is provided to significantly reduce susceptibility to collector commutation. All inputs are
diode clamped to reduce the effects of line ringing. The counters have parallel from each counter stage
so that submultiples of the input count frequency are available for system timing signals.
Rochester Electronics
Manufactured Components
Rochester branded components are
manufactured using either die/wafers
purchased from the original suppliers
or Rochester wafers recreated from the
original IP. All recreations are done with
the approval of the OCM.
Parts are tested using original factory
test programs or Rochester developed
test solutions to guarantee product
meets or exceeds the OCM data sheet.
Quality Overview
• ISO-9001
• AS9120 certification
• Qualified Manufacturers List (QML) MIL-PRF-38535
• Class Q Military
• Class V Space Level
• Qualified Suppliers List of Distributors (QSLD)
• Rochester is a critical supplier to DLA and
meets all industry and DLA standards.
Rochester Electronics, LLC is committed to supplying
products that satisfy customer expectations for
quality and are equal to those originally supplied by
industry manufacturers.
The original manufacturer’s datasheet accompanying this document reflects the performance
and specifications of the Rochester manufactured version of this device. Rochester Electronics
guarantees the performance of its semiconductor products to the original OEM specifications.
‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be
based on product characterization, design, simulation, or sample testing.
© 2014 Rochester Electronics, LLC. All Rights Reserved 01282014
To learn more, please visit
www.rocelec.com
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
D
D
D
D
D
D
1CLR
1CLK
NC
V
CC
description
Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to
implement two individual 4-bit decade counters in
a single package. Each decade counter has
individual clock (1CLK, 2CLK), clear (1CLR,
2CLR), and set-to-9 (1SET9, 2SET9) inputs. BCD
count sequences of any length up to
divide-by-100 can be implemented with a single
’LS490 device. Buffering on each output is
provided to significantly reduce susceptibility to
collector commutation. All inputs are diode
clamped to reduce the effects of line ringing. The
counters have parallel outputs from each counter
stage so that submultiples of the input count
frequency are available for system timing signals.
1Q
A
1SET9
NC
1Q
B
1Q
C
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2CLK
2CLR
2Q
A
NC
2SET9
2Q
B
Dual Versions of the SN54LS90 and
SN74LS90 Counters
Individual Clock, Direct Clear, and Set-to-9
Inputs for Each Decade Counter
Dual Counters Can Significantly Improve
System Densities as Package Count Can
Be Reduced by 50%
Maximum Count Frequency of
25 MHz . . . 35 MHz Typical
Buffered Outputs Reduce Possibility of
Collector Commutation
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
SN54LS490 . . . J OR W PACKAGE
SN74LS490 . . . D OR N PACKAGE
(TOP VIEW)
1CLK
1CLR
1Q
A
1SET9
1Q
B
1Q
C
1Q
D
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
2CLK
2CLR
2Q
A
2SET9
2Q
B
2Q
C
2Q
D
SN54LS490 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
The SN54LS490 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LS490 is characterized for use in industrial systems operating from 0°C to 70°C.
CLEAR/SET-TO-9 FUNCTION TABLE
(each counter)
INPUTS
CLR
H
L
L
SET9
L
H
L
QA
L
H
OUTPUTS
QB
L
L
Count
QC
L
L
QD
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
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1Q
D
GND
NC
2Q
D
2Q
C
1
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
BCD COUNT SEQUENCE
(each counter)
COUNT
0
1
2
3
4
5
6
7
8
9
OUTPUTS
QD
L
L
L
L
L
L
L
L
H
H
QC
L
L
L
L
H
H
H
H
L
L
QB
L
L
H
H
L
L
H
H
L
L
QA
L
H
L
H
L
H
L
H
L
H
logic symbol
†
CTRDIV10
1CLR
1SET9
1CLK
2
4
1
CT=0
CT=9
+
3
CT
0
3
5
6
7
1QA
1QB
1QC
1QD
2CLR
2SET9
2CLK
14
12
15
13
11
10
9
2QA
2QB
2QC
2QD
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
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SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
schematics of inputs and outputs
EQUIVALENT OF
EACH CLK INPUT
VCC
43 kΩ NOM
EQUIVALENT OF
EACH CLR AND SET9 INPUT
VCC
18 kΩ NOM
Input
TYPICAL OF
ALL OUTPUTS
VCC
120
Ω
NOM
Input
Output
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3
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
logic diagram (each counter)
4, 12
SET9
S
CLK
1, 15
T
R
3, 13
QA
5, 11
T
R
QB
6, 10
T
R
QC
S
T
R
7, 9
QD
CLR
2, 14
Pin numbers shown are for the D, J, N, and W packages.
4
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