8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
DRAM
MODULE
FEATURES
• JEDEC-standard ECC pinout in a 168-pin, dual in-
line memory module (DIMM)
• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (32 Meg x 72)
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs, and clocks are LVTTL-compatible
• All inputs are buffered except RAS#
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• Extended Data-Out (EDO) PAGE MODE access cycle
MT9LD(T)872(F)X, MT18LD(T)1672(F)(D)X,
MT36LD(T)3272(C)(F)X
For the latest data sheet, please refer to the Micron Web site:
www.micronsemi.com/datasheets/datasheet.html
PIN ASSIGNMENT
OPTIONS
• Components
SOJ
TSOP
• Package
168-pin DIMM (gold)
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
• Module Height
Low profile, 1.65" (256MB only)
Low profile, 1.25" (128MB only)
• Timing
50ns access
60ns access
• Access Cycle
EDO PAGE MODE
MARKING
D
DT
G
Blank
F
C
D
-5
-6
X
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
30ns
35ns
18ns
20ns
8ns
10ns
Front View (128MB)
168-PIN DIMM
PIN SYMBOL PIN
1
V
SS
43
2
DQ0
44
3
DQ1
45
4
DQ2
46
5
DQ3
47
6
V
DD
48
7
DQ4
49
8
DQ5
50
9
DQ6
51
10
DQ7
52
11
DQ8
53
12
V
SS
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
V
DD
60
19
DQ14
61
20
DQ15
62
21
DQ16
63
22
DQ17
64
23
V
SS
65
24
NC
66
25
NC
67
26
V
DD
68
27
WE0#
69
28
CAS0#
70
29
RFU
71
30
RAS0#
72
31
OE0#
73
32
V
SS
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
A10
80
39
A12
81
40
V
DD
82
41
RFU
83
42
RFU
84
*256MB version only
SYMBOL
V
SS
OE2#
RAS2#
CAS4#
RFU
WE2#
V
DD
NC
NC
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
DD
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
DD
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
DD
PIN SYMBOL PIN SYMBOL
85
V
SS
127
V
SS
86
DQ36
128
RFU
87
DQ37
129 NC/RAS3#*
88
DQ38
130 NC/CAS5#*
89
DQ39
131
RFU
90
V
DD
132
PDE#
91
DQ40
133
V
DD
92
DQ41
134
NC
93
DQ42
135
NC
94
DQ43
136
DQ54
95
DQ44
137
DQ55
96
V
SS
138
V
SS
97
DQ45
139
DQ56
98
DQ46
140
DQ57
99
DQ47
141
DQ58
100
DQ48
142
DQ59
101
DQ49
143
V
DD
102
V
DD
144
DQ60
103
DQ50
145
RFU
104
DQ51
146
RFU
105
DQ52
147
RFU
106
DQ53
148
RFU
107
V
SS
149
DQ61
108
NC
150
DQ62
109
NC
151
DQ63
110
V
DD
152
V
SS
111
RFU
153
DQ64
112 NC/CAS1#*
154
DQ65
113
RFU
155
DQ66
114 NC/RAS1#*
156
DQ67
115
RFU
157
V
DD
116
V
SS
158
DQ68
117
A1
159
DQ69
118
A3
160
DQ70
119
A5
161
DQ71
120
A7
162
V
SS
121
A9
163
PD2
122
A11
164
PD4
123 NC (A13) 165
PD6
124
V
DD
166
PD8
125
RFU
167
ID1
126
B0
168
V
DD
NOTE:
Pin symbols in parentheses are not used on these
modules but may be used for other modules in this
product family. They are for reference only.
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
PART NUMBERS
PART NUMBER
MT9LD872G-x X
MT9LDT872G-x X
MT9LD872FG-x X
MT9LDT872FG-x X
MT18LD1672G-x X
MT18LDT1672G-x X
MT18LD1672FG-x X
MT18LDT1672FG-x X
MT18LDT1672FDG-x X
MT36LD3272G-x X
MT36LDT3272G-x X
MT36LD3272FG-x X
MT36LDT3272FG-x X
MT36LD3272CG-x X
MT36LD3272CFG-x X
x = speed
CONFIGURATION
8 Meg x 72 ECC
8 Meg x 72 ECC
8 Meg x 72 ECC
8 Meg x 72 ECC
16 Meg x 72 ECC
16 Meg x 72 ECC
16 Meg x 72 ECC
16 Meg x 72 ECC
16 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
REFRESH
ADDRESSING
4K
4K
8K
8K
4K
4K
8K
8K
8K
4K
4K
8K
8K
4K
8K
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGE-
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back HIGH.
EDO provides for CAS# precharge time (
t
CP) to occur
without the output data going invalid. This elimina-
tion of CAS# output control provides for pipeline READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE# is
pulsed while RAS# and CAS# are LOW, data will toggle
from valid data to High-Z and back to the same valid
data. If OE# is toggled or pulsed after CAS# goes HIGH
while RAS# remains LOW, data will transition to and
remain High-Z.
During an application, if the DQ outputs are wire
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also tristate the outputs. Indepen-
dent of OE# control, the outputs will disable after
t
OFF,
which is referenced from the rising edge of RAS# or
CAS#, whichever occurs last. (Refer to the
MT4LC16M4H9 DRAM data sheet for additional infor-
mation on EDO functionality.)
GENERAL DESCRIPTION
The Micron
®
MT9LD(T)872(F)X, MT18LD(T)1672(F)X,
and MT36LD(T)3272(F)X are randomly accessed 64MB,
128MB, and 256MB memories organized in a x72 con-
figuration. They are specially processed to operate from
3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits. First, the row ad-
dress is latched by the RAS# signal, then the column
address by CAS#. Two copies of address 0 (A0 and B0)
are defined to allow maximum performance for 4-byte
applications which interleave between two 4-byte banks.
A0 is common to the DRAMs used for DQ0-DQ35, while
B0 is common to the DRAMs used for DQ36-DQ71.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. EARLY WRITE
occurs when WE# goes LOW prior to CAS# going LOW,
and the output pins remain open (High-Z) until the
next CAS# cycle.
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and execut-
ing any RAS# cycle (READ, WRITE) or RAS# REFRESH
cycle (RAS#-ONLY, CBR or HIDDEN) so that all 4,096
combinations of RAS# addresses (A0-A11) are executed
at least every 64ms, regardless of sequence. However,
with the RAS#-ONLY REFRESH method some compat-
ibility issues may become apparent (128MB and 256MB
versions only). For example, both 4K and 8K refresh
options require 4,096 CBR REFRESH cycles, yet require
a different number of RAS#-ONLY REFRESH cycles (4K
= 4,096 and 8K = 8,192). JEDEC strongly recommends
the use of CBR REFRESH for these devices. The CBR
REFRESH cycle will invoke the internal refresh counter
for automatic RAS# addressing.
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT9LD(T)872(F)X (64MB)
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
DQ32-DQ39
A0
WE0#
OE0#
RAS0#
CAS0#
D
D
D
A0
WE#
DQ0-DQ7
A0
WE#
DQ0-DQ7
A0
WE#
DQ0-DQ7
A0
WE#
DQ0-DQ7
A0
WE#
DQ0-DQ7
U0
OE#
RAS#
OE#
RAS#
U1
OE#
RAS#
U2
OE#
RAS#
U3
OE#
RAS#
U4
D
CAS#
A1–A11
CAS#
A1–A11
CAS#
A1–A11
CAS#
A1–A11
CAS#
A1–A11
A11
A12-A1
D
A1
DQ40-DQ47
DQ48-DQ55
DQ56-DQ63
DQ64-DQ71
B0
WE2#
OE2#
RAS2#
CAS4#
D
D
D
A0
WE#
DQ0-DQ7
A0
WE#
DQ0-DQ7
A0
WE#
DQ0-DQ7
A0
WE#
DQ0-DQ7
U5
OE#
RAS#
OE#
RAS#
U6
OE#
RAS#
U7
OE#
RAS#
U8
D
CAS#
A1–A11
CAS#
A1–A11
CAS#
A1–A11
CAS#
A1–A11
PRESENCE
DETECT
GENERATOR
PD1-PD8
U0-U8 = MT4LC8M8C2DJ EDO PAGE MODE, SOJ, 4K REFRESH
U0-U8 = MT4LC8M8C2TG EDO PAGE MODE, TSOP, 4K REFRESH
U0-U8 = MT4LC8M8P4DJ EDO PAGE MODE, SOJ, 8K REFRESH
E#
PDE#
V
DD
V
SS
U0-U8, BUFFERS
U0-U8, BUFFERS
U0-U8 = MT4LC8M8P4TG EDO PAGE MODE, TSOP, 8K REFRESH
NOTE:
1. All inputs with the exception of RAS# are redriven.
2. D = line buffers.
3. Reference designators in this diagram do not necessarily match the actual module.
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT18LD(T)1672(F)X (128MB)
DQ0-DQ3
DQ4-DQ7
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ32-DQ35
A0
WE0#
OE0#
RAS0#
CAS0#
D
D
D
A0 DQ0-DQ3
WE#
U0
OE#
RAS#
A0 DQ0-DQ3
WE#
U1
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U2
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U3
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U4
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U5
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U6
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U7
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U8
OE#
RAS#
CAS# A1–A11
D
CAS# A1–A11
A11
A12-A1
D
A1
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ64-DQ67
DQ68-DQ71
B0
WE2#
OE2#
RAS2#
CAS4#
D
D
D
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0 DQ0-DQ3
WE#
U16
OE#
RAS#
CAS# A1–A11
A0
DQ0-DQ3
WE#
U9
OE#
RAS#
WE#
U10
OE#
RAS#
CAS# A1–A11
WE#
U11
OE#
RAS#
CAS# A1–A11
WE#
U12
OE#
RAS#
CAS# A1–A11
WE#
U13
OE#
RAS#
CAS# A1–A11
WE#
U14
OE#
RAS#
CAS# A1–A11
WE#
U15
OE#
RAS#
CAS# A1–A11
WE#
U17
OE#
RAS#
CAS# A1–A11
D
CAS# A1–A11
PRESENCE-
DETECT
GENERATOR
E#
PDE#
PD1-PD8
U0-U17 = MT4LC16M4H9DJ EDO PAGE MODE, SOJ, 4K REFRESH
U0-U17 = MT4LC16M4H9TG EDO PAGE MODE, TSOP, 4K REFRESH
U0-U17 = MT4LC16M4G3DJ EDO PAGE MODE, SOJ, 8K REFRESH
V
DD
V
SS
U0-U17, BUFFERS
U0-U17, BUFFERS
U0-U17 = MT4LC16M4G3TG EDO PAGE MODE, TSOP, 8K REFRESH
NOTE:
1. All inputs with the exception of RAS# are redriven.
2. D = line buffers.
3. Reference designators in this diagram do not necessarily match the actual module.
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT36LD(T)3272(C)(F)X (256MB)
DQ0-DQ3
DQ4-DQ7
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ32-DQ35
A0
WE0#
OE0#
RAS0#
CAS0#
D
D
D
A0 DQ0-DQ3
WE#
U0
OE#
RAS#
A0 DQ0-DQ3
WE#
U1
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U2
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U3
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U4
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U5
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U6
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U7
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U8
OE#
RAS#
CAS# A1–A11
D
CAS# A1–A11
11
11
11
11
11
11
11
11
11
A11
A11-A1
D
A1
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ64-DQ67
DQ68-DQ71
B0
WE2#
OE2#
RAS2#
CAS4#
D
D
D
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0 DQ0-DQ3
WE#
U13
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U14
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U15
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U16
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U17
OE#
RAS#
CAS# A1–A11
WE#
U9
OE#
RAS#
WE#
U10
OE#
RAS#
CAS# A1–A11
WE#
U11
OE#
RAS#
CAS# A1–A11
WE#
U12
OE#
RAS#
CAS# A1–A11
D
CAS# A1–A11
11
11
11
11
11
11
11
11
11
DQ0-DQ3
DQ4-DQ7
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ32-DQ35
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0 DQ0-DQ3
WE#
A0 DQ0-DQ3
WE#
A0 DQ0-DQ3
WE#
A0 DQ0-DQ3
WE#
A0 DQ0-DQ3
WE#
WE#
U18
OE#
WE#
U19
OE#
RAS#
CAS# A1–A11
WE#
U20
OE#
RAS#
CAS# A1–A11
WE#
U21
OE#
RAS#
CAS# A1–A11
U22
OE#
RAS#
CAS# A1–A11
OE#
RAS#
U23
OE#
RAS#
U24
OE#
RAS#
U25
OE#
RAS#
U26
RAS1#
CAS1#
D
RAS#
CAS# A1–A11
CAS# A1–A11
CAS# A1–A11
CAS# A1–A11
CAS# A1–A11
11
11
11
11
11
11
11
11
11
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ64-DQ67
DQ68-DQ71
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0
DQ0-DQ3
A0 DQ0-DQ3
WE#
U31
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U32
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U33
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U34
OE#
RAS#
CAS# A1–A11
A0 DQ0-DQ3
WE#
U35
OE#
RAS#
CAS# A1–A11
WE#
U27
OE#
WE#
U28
OE#
RAS#
CAS# A1–A11
WE#
U29
OE#
RAS#
CAS# A1–A11
WE#
U30
OE#
RAS#
CAS# A1–A11
RAS3#
CAS5#
D
RAS#
CAS# A1–A11
11
11
11
11
11
11
11
11
11
PRESENCE-
DETECT
GENERATOR
PD1-PD8
U0-U35 = MT4LC16M4T8DJ EDO PAGE MODE, SOJ, 4K REFRESH
U0-U35 = MT4LC16M4T8TG EDO PAGE MODE, TSOP, 4K REFRESH
U0-U35 = MT4LC16M4A7DJ EDO PAGE MODE, SOJ, 8K REFRESH
E#
PDE#
V
DD
V
SS
U0-U35, BUFFERS
U0-U35, BUFFERS
U0-U35 = MT4LC16M4A7TG EDO PAGE MODE, TSOP, 8K REFRESH
NOTE:
1. All inputs with the exception of RAS# are redriven.
2. D = line buffers.
3. Reference designators in this diagram do not necessarily match the actual module.
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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