128MB, 256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
DDR SDRAM
SMALL-OUTLINE DIMM
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Supports ECC error detection and correction
• Fast data transfer rates: PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
• 128MB (16 Meg x 72), 256MB (32 Meg x 72), 512MB
(64 Meg x 72), and 1GB (128 Meg x 72)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs (128MB) or 7.8125µs (256MB, 512MB,
1GB) maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
MT9VDDT1672H – 128MB,
MT9VDDT3272H – 256MB,
MT9VDDT6472H – 512MB,
MT9VDDT12872H – 1GB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 200-Pin SODIMM (MO-224)
1.25in. (31.75mm)
OPTIONS
MARKING
• Operating Temperature Range
Commercial (0°C
≤
T
A
≤
+70°C)
None
Industrial (-40°C
≤
T
A
≤
+85°C)
I
2
• Package
200-pin SODIMM (standard)
G
200-pin SODIMM (lead-free)
Y
2
• Memory clock, Speed, CAS Latency
1
6.0ns (167 MHz), 333 MT/s, CL = 2.5
-335
7.5ns (133 MHz), 266 MT/s, CL = 2
-262
2
7.5ns (133 MHz), 266 MT/s, CL = 2
-26A
2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
-265
10ns (100 MHz), 200 MT/s, CL = 2
-202
2
• PCB
1.25in. (31.75mm)
See page 2 note
NOTE:
1. CL = Device CAS (READ) Latency.
2. Consult Micron for product availability.
Table 1:
Address Table
128MB
256MB
512MB
1GB
8K
16K (A0–A13)
4 (BA0, BA1)
1Gb (128 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
4K
8K
8K
8K (A0–A11)
8K (A0–A12)
8K (A0–A12)
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8)
1K (A0–A9)
1K (A0–A9)
2K (A0–A9, A11)
1 (S0#)
1 (S0#)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef80804052, source: 09005aef806e057b
DD9C16_32_64_128x72HG.fm - Rev. B 9/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
CONFIGURATION
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
MODULE
BANDWIDTH
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
MEMORY CLOCK/
DATA RATE
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
PART NUMBER
MT9VDDT1672H(I)G-335__
MT9VDDT1672H(I)Y-335__
MT9VDDT1672H(I)G-262__
MT9VDDT1672H(I)Y-262__
MT9VDDT1672H(I)G-26A__
MT9VDDT1672H(I)Y-26A__
MT9VDDT1672H(I)G-265__
MT9VDDT1672H(I)Y-265__
MT9VDDT1672H(I)G-202__
MT9VDDT1672H(I)Y-202__
MT9VDDT3272H(I)G-335__
MT9VDDT3272H(I)Y-335__
MT9VDDT3272H(I)G-262__
MT9VDDT3272H(I)Y-262__
MT9VDDT3272H(I)G-26A__
MT9VDDT3272H(I)Y-26A__
MT9VDDT3272H(I)G-265__
MT9VDDT3272H(I)Y-265__
MT9VDDT3272H(I)G-202__
MT9VDDT3272H(I)Y-202__
MT9VDDT6472H(I)G-335__
MT9VDDT6472H(I)Y-335__
MT9VDDT6472H(I)G-262__
MT9VDDT6472H(I)Y-262__
MT9VDDT6472H(I)G-26A__
MT9VDDT6472H(I)Y-26A__
MT9VDDT6472H(I)G-265__
MT9VDDT6472H(I)Y-265__
MT9VDDT6472H(I)G-202__
MT9VDDT6472H(I)Y-202__
MT9VDDT12872H(I)G-335__
MT9VDDT12872H(I)Y-335__
MT9VDDT12872H(I)G-262__
MT9VDDT12872H(I)Y-262__
MT9VDDT12872H(I)G-26A__
MT9VDDT12872H(I)Y-26A__
MT9VDDT12872H(I)G-265__
MT9VDDT12872H(I)Y-265__
MT9VDDT12872H(I)G-202__
MT9VDDT12872H(I)Y-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9VDDT3272HG-265A1.
pdf: 09005aef80804052, source: 09005aef806e057b
DD9C16_32_64_128x72HG.fm - Rev. B 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
51
53
55
57
V
SS
DQ19
DQ24
V
DD
101
103
105
107
109
A9
Vss
A7
A5
A3
151
153
155
157
159
DQ42
DQ43
Vdd
Vdd
V
SS
Table 4:
Pin Assignment
(200-pin SODIMM Back)
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
CB4
CB5
V
SS
DM8
CB6
V
DD
CB7
NC
V
SS
V
SS
V
DD
V
DD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
RAS#
CAS#
NC
NC
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
V
DD
CK1#
CK1
V
SS
DQ52
DQ53
V
DD
DM6
DQ54
V
SS
DQ55
DQ60
V
DD
DQ61
DM7
V
SS
DQ62
DQ63
V
DD
SA0
SA1
SA2
NC
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
DQ21
V
DD
DM2
DQ22
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0#
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
59
DQ25
61
DQS3
63
V
SS
65
DQ26
67
DQ27
69
V
DD
71
CB0
73
CB1
75
V
SS
77
DQS8
79
CB2
81
V
DD
83
CB3
85
NC
87
V
SS
89
CK2
91
CK2#
93
V
DD
95
NC
97
NC
99
NC/A12
1
111
A1
113
V
DD
115
A10
117
BA0
119
WE#
121
S0#
123
NC/A13
2
125
V
SS
127 DQ32
129 DQ33
131
V
DD
133 DQS4
135 DQ34
137
V
SS
139 DQ35
141 DQ40
143
V
DD
145 DQ41
147 DQS5
149
V
SS
161
V
SS
163 DQ48
165 DQ49
167
V
DD
169 DQS6
171 DQ50
173
V
SS
175 DQ51
177 DQ56
179
V
DD
181 DQ57
183 DQS7
185
V
SS
187 DQ58
189 DQ59
191
V
DD
193
SDA
195
SCL
197 V
DDSPD
199
NC
1. Pin 99 is NC for 128MB and A12 for 256MB, 512MB, and 1GB.
2. Pin 123 is NC for 128MB, 256MB, and 512MB and A13 for 1GB.
Figure 2: Module Layout
Front View
Back View
U8
U1
U2
U3
U4
U5
U6
U7
U9
U10
PIN 1
(all odd pins)
PIN 199
PIN 200
(all even pins)
PIN 2
Indicates a VDD or VDDQ pin
Indicates a VSS pin
pdf: 09005aef80804052, source: 09005aef806e057b
DD9C16_32_64_128x72HG.fm - Rev. B 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#, RAS#
CK0, CK0#, CK1,
CK1#, CK2, CK2#
TYPE
Input
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
118, 119, 120
35, 37, 89, 91, 158, 160
96
CKE0
121
S0#
116, 117
99
(256MB, 512MB, 1GB),
100, 101, 102, 105, 106, 107,
108, 109, 110, 111, 112, 115,
123
(1GB)
BA0, BA1
A0–A11
(128MB)
A0–A12
(256MB, 512MB)
A0–A13
(1GB)
11, 25, 47, 61, 77, 133, 147,
169, 183
12, 26, 48, 62, 78, 134, 148,
170, 184
DQS0–DQS8
DM0–DM8
71,72, 73, 74, 79, 80, 83, 84
5–8, 13–20, 23–24, 29–32,
41–44, 49–50, 53–56, 59–60,
65–68, 127–130, 135–136,
139–142, 145–146, 151–154,
163–166, 171–172, 175–178,
181–182, 187–190
CB0–CB7
DQ0–DQ63
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any device bank).CKE is synchronous for POWER-
DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
DD
is applied.
Input Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Input Bank Address: BA0, BA1 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Input Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs also
provide the op-code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register (mode register or
extended mode register) is loaded during the LOAD MODE
REGISTER command.
Input/ Data Strobe: Output with READ data, input with WRITE data.
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Input/ Check Bits.
Output
Input/ Data I/Os: Data bus.
Output
pdf: 09005aef80804052, source: 09005aef806e057b
DD9C16_32_64_128x72HG.fm - Rev. B 9/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions (Continued)
SYMBOL
SCL
SA0–SA2
SDA
TYPE
Input
Input
Input/
Output
Supply
Supply
DESCRIPTION
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
SSTL_2 reference voltage.
Power Supply: +2.5V ±0.2V.
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
195
194, 196, 198
193
1, 2
9–10, 21–22, 33–34, 36, 45–
46, 57–58, 69–70, 81–82,
92–94, 113–114, 131–132,
143–144, 155–157, 167–168,
17–180, 191–192
3–4 15–16, 27–28, 38–40,
51–52, 63–64, 75–76, 87–88,
90, 103–104, 125–126,
137–138, 149–150, 159,
161–162, 173–174, 185–186
197
85, 95, 97, 122,
123 (128MB, 256MB,
512MB), 199 (128MB),
98, 124, 200
V
REF
V
DD
V
SS
Supply Ground.
V
DDSPD
NC
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
—
No Connect: These pins should be left unconnected.
pdf: 09005aef80804052, source: 09005aef806e057b
DD9C16_32_64_128x72HG.fm - Rev. B 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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