ADVANCE INFORMATION
GALVANTECH
, INC.
SYNCHRONOUS
CACHE TAG SRAM
PIPELINED OUTPUT
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fast match times: 4.5, 5.0, 6.0, and 7.0ns
Fast clock speed: 133, 100, 83, and 75 MHz
Fast OE# access times: 4.5ns and 5.0ns
Pipelined data comparator
Data input register load control by DEN#
3.3V -5% and +10% power supply
5V tolerant inputs except I/O’s
Clamp diodes to VSS at all inputs and outputs
Common data inputs and data outputs
Two chip enables for depth expansion
Address, data and control registers
Internally self-timed WRITE CYCLE
Automatic power-down for portable applications
Low profile 119 lead, 14mm x 22mm BGA (Ball Grid
Array) and 100 pin TQFP packages
GVT7164T18
64K X 18 SYNCHRONOUS TAG SRAM
64K x 18 SRAM
+3.3V SUPPLY WITH CLOCKED
REGISTERED INPUTS
GENERAL DESCRIPTION
The Galvantech Synchronous SRAM family employs
high-speed, low power CMOS designs using advanced triple-
layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The GVT7164T18 SRAM integrates 65,536 x 18 SRAM
cells with advanced synchronous peripheral circuitry and a
18-bit comparator for tag compare operation. All synchronous
inputs are gated by registers controlled by a positive-edge-
triggered clock input (CLK). The synchronous inputs include
all addresses, all data inputs, depth-expansion chip enables
(CE# and CE1), write enable (WE#), and data input enable
(DEN#).
Asynchronous inputs include the output enable (OE#)
and the match output enable (MOE#). The data outputs (Q)
and match output (MATCH), enabled by OE# and MOE#
respectively, are also asynchronous.
Data inputs are registered with data input enable (DEN#)
and chip enable pins (CE#, CE1). The outputs of the data
input registers are compared with data in the memory array
and a match signal is generated. The match output is gated
into a pipeline register and released to the match output pin at
the next rising edge of clock (CLK).
The GVT7164T18 operates from a +3.3V power supply.
All inputs and outputs are LVTTL compatible. The device is
ideally suited for address tag RAM for up to 2 MB secondary
cache.
OPTIONS
•
Timing
4.5ns access/7.5ns cycle
5.0ns access/10ns cycle
6.0ns access/12ns cycle
7.0ns access/13.3ns cycle
Packages
119-lead BGA
100-pin TQFP
MARKING
-4
-5
-6
-7
B
T
•
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 11/97
Galvantech, Inc. reserves the right to change
products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH
, INC.
FUNCTIONAL BLOCK DIAGRAM
WRITE
GVT7164T18
64K X 18 SYNCHRONOUS TAG SRAM
WE#
D
Q
D
Q
OE#
MATCH
MOE#
D
Q
CE#
CE1
Latch
ENABLE
D
Q
Compare
DEN#
Latch
A
CLK
16
Address
Register
Input
Register
64K x 9 x 2
SRAM Array
OUTPUT
REGISTER
Output Buffers
D
Q
DQ1-
DQ18
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing
diagrams for detailed information.
November 5, 1997
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 11/97
ADVANCE INFORMATION
GALVANTECH
, INC.
GVT7164T18
64K X 18 SYNCHRONOUS TAG SRAM
PIN ASSIGNMENTS (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCC
2
A
3
A
4
NC
NC
5
A
6
7
A
A
CE#
CE1
NC
NC
NC
NC
NC
VCC
VSS
CLK
NC
WE#
OE#
NC
NC
NC
A
A
100 99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
NC
VCC
NC
NC
NC
VCC
VSS
NC
NC
DQ10
DQ11
VSS
VCC
DQ12
DQ13
NC
VCC
NC
VSS
DQ14
DQ15
VCC
VSS
DQ16
DQ17
DQ18
NC
VSS
VCC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC CE1 NC
NC
DQ
10
NC CE# NC
NC
NC
VCC
A
A
NC
NC VSS NC VSS DQ9 NC
NC
DQ
11
VSS NC VSS NC DQ8
VCC
NC VSS OE# VSS DQ7
VCC
NC VSS NC DQ6
NC
DQ
12
NC
DQ
13
100-pin TQFP
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC VSS
WE#
VSS DQ5 NC
NC
VCC
VCC VCC
NC
VCC VCC
NC
DQ
14
VSS CLK VSS NC DQ4
DQ
15
NC VSS NC
NC DQ3 NC
VCC DQ
16
VSS
DQ
17
NC VSS NC
VCC
A
NC
NC
VCC
VSS
NC
DQ9
DQ8
DQ7
VSS
VCC
DQ6
DQ5
VSS
NC
VCC
NC
DQ4
DQ3
VCC
VSS
DQ2
DQ1
NC
NC
VSS
VCC
NC
NC
NC
NC VSS
A
A
VCC
MATCH
VSS DQ2 NC
VSS NC DQ1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQ
18
VSS
NC
NC
VCC
A
A
DEN#
A
A
NC
A
A
MOE#
A
A
NC
NC
A
NC
VCC
TOP VIEW 119 LEAD BGA
November 5, 1997
3
Rev. 11/97
NC
A
A
A
A
A
A
VSS
MATCH
VSS
VCC
DEN#
MOE#
A
A
A
A
A
NC
NC
Galvantech, Inc. reserves the right to change products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH
, INC.
PIN DESCRIPTIONS
BGA PINS
TQFP PINS
SYMBOL
A
GVT7164T18
64K X 18 SYNCHRONOUS TAG SRAM
TYPE
Input-
DESCRIPTION
Addresses: These inputs are registered and must meet the
2A, 3A, 5A, 5C, 6C, 4N, 37, 36, 35, 34, 33, 32, 100,
4P, 2R, 3R, 5R, 6R, 2T, 3T, 99, 82, 81, 80, 48, 47, 46,
5T, 6T, 4U
45, 44
4H
87
Synchronous
setup and hold times around the rising edge of CLK.
WE#
Input-
Write Enable: this write enable is LOW for a WRITE cycle
one cycle after WE#=LOW is gated into register.
Synchronous
and HIGH for a READ cycle. Data I/O are high impedance
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip
its rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
Synchronous
enables, write control and data input enable control input on
6B
2B
4F
2U
4T
98
97
86
42
39
CE#
CE1
OE#
DEN#
MATCH
Chip Enable: This active LOW input is used to enable the
Synchronous
device.
input-
Input
Input-
Output
Chip enable: This active HIGH input is used to enable the
Output Enable: This active LOW asynchronous input
enables the data output drivers.
Data Input Enable: This active LOW input is used to control
Match Output: MATCH will be HIGH if data in the data input
registers match the data stored in the memory array,
assuming MOE# being LOW. MATCH will be LOW if data do
not match.
Match Output Enable: This active LOW asynchronous input
enables the MATCH output drivers.
Data Inputs/Outputs: Input data must meet setup and hold
times around the rising edge of CLK.
Power Supply: +3.3V -5% and +10%
Synchronous
device.
Input-
Synchronous
the update of data input registers.
5U
43
MOE#
DQ1-DQ18
Input
Input/
Output
Supply
7P, 6N, 6L, 7K, 6H, 7G, 6F, 58, 59, 62, 63, 68, 69, 72,
7E, 6D, 1D, 2E, 2G, 1H, 73, 74, 8, 9, 12, 13, 18, 19,
2K, 1L, 2M, 1N, 2P
22, 23, 24
1A, 7A, 4C, 1F, 7F, 1J, 2J,
4J, 6J, 7J, 1M, 7M, 4R,
1U, 7U
3D, 5D, 3E, 5E, 3F, 5F,
5G, 3H, 5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N, 3P, 5P
4A, 6A, 1B, 3B, 4B, 5B,
7B, 1C, 2C, 3C, 7C, 2D,
4D, 7D, 1E, 4E, 6E, 2F,
1G, 3G, 4G, 6G, 2H, 7H,
3J, 5J, 1K, 6K, 2L, 4L, 5L,
7L, 4M, 6M, 2N, 7N, 1P,
6P, 1R, 7R, 1T, 7T, 3U, 6U
4, 11, 15, 20, 27, 41, 54,
61, 65, 70, 77, 91
5, 10, 17, 21, 26, 38, 40,
55, 60, 67, 71, 76, 90
1-3, 6, 7, 14, 16, 25, 28-
31, 49-53, 56, 57, 64, 66,
75, 78, 79, 83-85, 88, 92-
96
VCC
VSS
Ground
Ground: GND.
NC
-
No Connect: These signals are not internally connected.
November 5, 1997
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 11/97
ADVANCE INFORMATION
GALVANTECH
, INC.
TRUTH TABLE
OPERATION
E#
WE#
DEN#
MOE##
GVT7164T18
64K X 18 SYNCHRONOUS TAG SRAM
OE#
MATCH
DQ
READ Cycle
WRITE Cycle
Fill WRITE Cycle
COMPARE Cycle
Deselected Cycle (MATCH Out)
Deselected Cycle
L
L
L
L
H
H
H
L
L
H
X
X
X
L
H
L
X
X
X
X
X
L
L
H
L
H
H
H
X
X
-
-
-
Output
H
High-Z
Q
D
High-Z
D
High-Z
High-Z
Note:
1.
2.
3.
4.
5.
X means “don’t care.” H means logic HIGH. L means logic LOW.
E# =L is defined as CE#=LOW and CE1=HIGH. E# =H is defined as CE#=HIGH or CE1=LOW.
All inputs except OE# and MOE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time
for OE# and staying HIGH throughout the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
THERMAL CHARACTERISTICS
DESCRIPTION
Thermal Resistance - Junction to Ambient
Thermal Resistance - Junction to Case
CONDITIONS
Still air, soldered on 4.25 x
1.125 inch 4-layer PCB
SYMBOL
Θ
JA
Θ
JC
BGA TYP
19
9
TQFP TYP
25
9
UNITS
o
C/W
o
C/W
NOTES
November 5, 1997
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 11/97
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