ADVANCE
‡
512Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micronsemi.com/datasheets/ddrsdramds.html
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
x4
x8
x16
V
DD
V
DD
V
DD
NC
DQ0
DQ0
V
DD
Q V
DD
Q
V
DD
Q
NC
DQ1
NC
DQ0
DQ1
DQ2
V
SS
Q
V
SS
Q
VssQ
NC
DQ3
NC
NC
DQ2
DQ4
V
DD
Q V
DD
Q
V
DD
Q
NC
NC
DQ5
DQ1
DQ3
DQ6
V
SS
Q
V
SS
Q
VssQ
NC
DQ7
NC
NC
NC
NC
V
DD
Q V
DD
Q
V
DD
Q
NC
NC
LDQS
NC
NC
NC
V
DD
V
DD
V
DD
DNU
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS#
CAS#
RAS#
RAS#
RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
V
DD
V
DD
V
DD
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x4
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
OPTIONS
MARKING
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4
64 Meg x 8 (16 Meg x 8 x 4 banks)
64M8
32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
• x16 IOL / IOH Drive
Full Drive Only
D1
Reduced Drive Only
D2
Programmable full or reduced drive
D3
• Plastic Package – OCPL
66-pin TSOP (standard 22.3mm length) T G
66-pin TSOP (extended 27mm length)
TH
(400 mil width, 0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2 (DDR266A
+
)
1
-7
2
7.5ns @ CL = 2.5 (DDR266B)
-75
3
-8
10ns @ CL = 2 (DDR200)
• Self Refresh
Standard
none
Low Power
L
NOTE:
1. Supports PC2100 modules with 2-2-2 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
TH Package
Configuration
Refresh Count
Row Addressing
BankAddressing
Column Addressing
128 Meg x 4
32 Meg x 4 x 4 banks
8K
8K(A0–A12)
4 (BA0, BA1)
4K(A0–A9,A11,A12)
64 Meg x 8
32 Meg x 16
16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
8K
8K(A0–A12)
4 (BA0, BA1)
2K(A0–A9, A11)
8K
8K(A0–A12)
4 (BA0, BA1)
1K(A0–A9)
KEY TIMING PARAMETERS
SPEED
GRADE
-7
-75
-8
CLOCK RATE
CL = 2**
133 MHz
100 MHz
100 MHz
CL = 2.5**
143 MHz
133 MHz
125 MHz
DATA-OUT
2.5ns
2.5ns
3.4ns
ACCESS
±0.75ns
±0.75ns
±0.8ns
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.6ns
WINDOW* WINDOW
*Minimum clock rate @ CL = 2 (-7, -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
TG Package
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
256Mb DDR SDRAM PART NUMBERS
(Note: xx= 7, 75, or 8)
PART NUMBER
MT46V128M4TH-xx
MT46V128M4TH-xxL
MT46V64M8TH-xx
MT46V64M8TH-xxL
MT46V32M16D1TH-xx
MT46V32M16D1TH-xxL
MT46V32M16D2TH-xx
MT46V32M16D2TH-xxL
MT46V32M16D3TH-xx
MT46V32M16D3TH-xxL
CONFIGURATION
128 Meg x 4
128 Meg x 4
64 Meg x 8
64 Meg x 8
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
I/O DRIVE LEVEL
Full Drive
Full Drive
Full Drive
Full Drive
Full Drive
Full Drive
Reduced Drive
Reduced Drive
Programmable Drive
Programmable Drive
REFRESH OPTION
Standard
Low Power
Standard
Low Power
Standard
Low Power
Standard
Low Power
Standard
Low Power
PACKAGE
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
GENERAL DESCRIPTION
The 512Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-
bank DRAM.
The 512Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 512Mb DDR SDRAM effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding
n-bit
wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.
The 512Mb DDR SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive strength outputs are SSTL_2, Class II compatible.
NOTE:
1. The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
2. Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, the x16
is divided in to two bytes—the lower byte and upper
byte. For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS; and for the
upper byte (DQ8 through DQ15) DM refers to UDM
and DQS refers to UDQS.
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
TABLE OF CONTENTS
Functional Block Diagram – 128 Meg x 4 .............
Functional Block Diagram – 64 Meg x 8 ...............
Functional Block Diagram – 32 Meg x 16 .............
Pin Descriptions ......................................................
Functional Description
.........................................
Initialization ......................................................
Register Definition .............................................
Mode Register ...............................................
Burst Length ............................................
Burst Type ................................................
Read Latency ...........................................
Operating Mode ......................................
Extended Mode Register ...............................
DLL Enable/Disable .................................
Commands
............................................................
Truth Table 1 (Commands)
.......................................
Truth Table 1A (DM Operation)
.................................
Deselect ..............................................................
No Operation (NOP) ..........................................
Load Mode Register ...........................................
Active ................................................................
Read ................................................................
Write ................................................................
Precharge ...........................................................
Auto Precharge ..................................................
Burst Terminate .................................................
Auto Refresh ......................................................
Self Refresh .........................................................
Operation
..............................................................
Bank/Row Activation .......................................
Reads ................................................................
Read Burst ....................................................
Consecutive Read Bursts ..............................
Nonconsecutive Read Bursts .......................
Random Read Accesses ................................
Terminating a Read Burst ............................
Read to Write ...............................................
Read to Precharge .........................................
Writes ................................................................
Write Burst ....................................................
Consecutive Write to Write .........................
Nonconsecutive Write to Write ..................
4
5
6
7
9
9
9
9
9
10
11
11
12
12
13
13
13
14
14
14
14
14
14
14
14
14
15
15
16
16
17
18
19
20
21
23
24
25
26
27
28
29
Random Writes ............................................
Write to Read – Uninterrupting ..................
Write to Read – Interrupting .......................
Write to Read – Odd, Interrupting .............
Write to Precharge – Uninterrupting ..........
Write to Precharge – Interrupting ...............
Write to Precharge – Odd, Interrupting ......
Precharge ...........................................................
Power-Down .....................................................
Truth Table 2 (CKE)
.................................................
Truth Table 3 (Current State, Same Bank)
.....................
Truth Table 4 (Current State, Different Bank)
.................
Operating Conditions
Absolute Maximum Ratings ....................................
DC Electrical and Operating Conditions .....................
AC Input Operating Conditions .............................
Capacitance – x4, x8 ..............................................
I
DD
Specifications and Conditions – x4, x8 ...........
Capacitance – x16 ..................................................
I
DD
Specifications and Conditions – x16 ...............
AC Electrical Characteristics (Timing Table) ..........
Slew Rate Derating Table .......................................
Data Valid Window Derating ...............................
Voltage and Timing Waveforms
Nominal Output Drive Curves .........................
Reduced Output Drive Curves (x16 only) ........
Output Timing –
t
DQSQ and
t
QH - x4, x8 ......
Output Timing –
t
DQSQ and
t
QH - x16 ..........
Output Timing –
t
AC and
t
DQSCK .................
Input Timing .....................................................
Input Voltage ....................................................
Initialize and Load Mode Registers ..................
Power-Down Mode ..........................................
Auto Refresh Mode ...........................................
Self Refresh Mode .............................................
Reads
Bank Read - Without Auto Precharge ........
Bank Read - With Auto Precharge ..............
Writes
Bank Write – Without Auto Precharge .......
Bank Write – With Auto Precharge .............
Write – DM Operation ................................
66-pin TSOP (TH) dimensions ...............................
66-pin TSOP (TG) dimensions ...............................
30
31
32
33
34
35
36
37
37
38
39
41
43
43
43
44
45
46
47
48
49
51
54
55
56
57
58
58
59
60
61
62
63
64
65
66
67
68
69
70
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
128 Meg x 4
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTERS
REFRESH 13
COUNTER
13
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
4
8
READ
LATCH
MUX
4
DQS
GENERATOR
COL0
4
CK
DATA
DLL
SENSE AMPLIFIERS
8192
DRVRS
1
DQ0 -
DQ3, DM
DQS
DQS
1
1
1
2
4
8
4
DATA
4
4
4
RCVRS
1
2
I/O GATING
DM MASK LOGIC
BANK
CONTROL
LOGIC
8
1
MASK
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
INPUT
REGISTERS
A0-A12,
BA0, BA1
15
ADDRESS
REGISTER
2
2048
(x8)
8
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
11
12
CK
1
1
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
64 Meg x 8
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTERS
REFRESH 13
COUNTER
13
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8192 x 1024 x 16)
8
16
READ
LATCH
MUX
8
DQS
GENERATOR
8
CK
DATA
DLL
SENSE AMPLIFIERS
8192
DRVRS
1
DQ0 -
DQ7, DM
DQS
DQS
1
1
1
2
8
16
8
DATA
8
8
8
RCVRS
1
2
I/O GATING
DM MASK LOGIC
BANK
CONTROL
LOGIC
16
1
MASK
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
INPUT
REGISTERS
A0-A12,
BA0, BA1
15
ADDRESS
REGISTER
2
1024
(x16)
16
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
10
11
CK
1
1
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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