DATASHEET
MS82C55A, MQ82C55A, MP82C55A
CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV).
The MX82C55A has identical features as the X82C55 with
the exception of no bus hold devices on the port pins. It is a
general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in two groups of
12 and used in three major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
FN6140
Rev 2.00
June 15, 2006
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
• Pin Compatible with OKI MSM82C55A
- No Bus Hold Devices on any Port Pins
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 8MHz 80C86
and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10A
Ordering Information
PART
NUMBERS*
(Note)
PART
MARKING
TEMP.
RANGE (°C)
0 to 70
0 to 70
-40 to 85
0 to 70
-40 to 85
44 Ld MQFP Q44.10x10
PACKAGE
(Pb-free)
PKG.
DWG. #
CMP82C55AZ CMP82C55AZ
CMS82C55AZ CMS82C55AZ
IMS82C55AZ
IMS82C55AZ
40 Ld PDIP** E40.6
44 Ld PLCC
N44.65
CMQ82C55AZ CMQ82C55AZ
IMQ82C55AZ IMQ82C55AZ
*Add “96” suffix to part number for tape and reel packaging.
**Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6140 Rev 2.00
June 15, 2006
Page 1 of 26
MS82C55A, MQ82C55A, MP82C55A
Pinouts
MS82C55A (PLCC)
TOP VIEW
RD
PA0
PA1
PA2
PA3
NC
PA4
PA5
PA6
PA7
WR
PA0
PA1
RD
MQ82C55A (MQFP)
TOP VIEW
PA2
PA3
PA4
PA5
PA6
PA7
WR
NC
6 5 4 3 2 1 44 43 42 41 40
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
7
8
9
10
11
12
13
14
15
16
17
18 1920 21 22 23 24 25 26 27 28
PC2
PC3
PB0
PB1
PB2
NC
PB3
PB4
PB5
PB6
PB7
39
38
37
36
35
34
33
32
31
30
29
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
V
CC
44 43 42 41 40 39 38 37 36 35 34
33
2
32
3
4
5
6
7
8
9
10
31
30
29
28
27
26
25
24
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
1
RESET
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
PB7
11
23
12 13 14 15 16 17 18 19 20 21 22
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
NC
NC
CMP82C55A (PDIP)
TOP VIEW
PA3 1
PA2 2
PA1 3
PA0 4
RD 5
CS 6
GND 7
A1 8
A0 9
PC7 10
PC6 11
PC5 12
PC4 13
PC0 14
PC1 15
PC2 16
PC3 17
PB0 18
PB1 19
PB2 20
40 PA4
39 PA5
38 PA6
37 PA7
36 WR
35 RESET
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 V
CC
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
FN6140 Rev 2.00
June 15, 2006
NC
Page 2 of 26
MS82C55A, MQ82C55A, MP82C55A
Pin Description
SYMBOL
V
CC
GND
D0-D7
RESET
CS
RD
WR
A0-A1
I/O
I
I
I
I
I
TYPE
DESCRIPTION
V
CC
: The +5V power supply pin. A 0.1F capacitor between V
CC
and GND is recommended for decoupling.
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PORT A: 8-bit input and output port.
PORT B: 8-bit input and output port.
PORT C: 8-bit input and output port.
PA0-PA7
PB0-PB7
PC0-PC7
I/O
I/O
I/O
Functional Diagram
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
GROUP A
PORT A
(8)
I/O
PA7-PA0
BIDIRECTIONAL
DATA BUS
D7-D0
DATA BUS
BUFFER
8-BIT
INTERNAL
DATA BUS
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
I/O
PC7-PC4
I/O
PC3-PC0
RD
WR
A1
A0
RESET
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PB7-PB0
CS
FIGURE 1. FUNCTIONAL DIAGRAM
FN6140 Rev 2.00
June 15, 2006
Page 3 of 26
MS82C55A, MQ82C55A, MP82C55A
Functional Description
Data Bus Buffer
This three-state bidirectional 8-bit buffer is used to interface the
82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information
are also transferred through the data bus buffer.
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
GROUP A
PORT A
(8)
I/O
PA7-
PA0
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words. It
accepts inputs from the CPU Address and Control busses and
in turn, issues commands to both of the Control Groups.
(CS)
Chip Select. A “low” on this input pin enables the
communication between the 82C55A and the CPU.
(RD)
Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
(WR)
Write. A “low” on this input pin enables the CPU to write
data or control words into the 82C55A.
(A0 and A1)
Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control the
selection of one of the three ports or the control word register.
They are normally connected to the least significant bits of the
address bus (A0 and A1).
82C55A BASIC OPERATION
A1
0
0
1
1
A0
0
1
0
1
RD
0
0
0
0
WR
1
1
1
1
CS
0
0
0
0
INPUT OPERATION
(READ)
Port A
Data
Bus
Port B
Data
Bus
Port C
Data
Bus
Control Word
Data
Bus
OUTPUT OPERATION
(WRITE)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Data Bus
Port
A
Data Bus
Port
B
Data Bus
Port
C
Data Bus
Control
DISABLE FUNCTION
X
X
X
X
X
1
X
1
1
0
Data Bus
Three-State
Data Bus
Three-State
BIDIRECTIONAL
DATA BUS
DATA
BUS
D7-D0
BUFFER
GROUP A
PORT C
UPPER
(4)
8-BIT
INTERNAL
DATA BUS
GROUP B
CONTROL
GROUP B
PORT C
LOWER
(4)
I/O
PC7-
PC4
I/O
PC3-
PC0
RD
WR
A1
A0
RESET
READ
WRITE
CONTROL
LOGIC
GROUP B
PORT B
(8)
I/O
PB7-
PB0
CS
FIGURE 2. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
Group A and Group B Controls
The functional configuration of each port is programmed by the
systems software. In essence, the CPU “outputs” a control
word to the 82C55A. The control word contains information
such as “mode”, “bit set”, “bit reset”, etc., that initializes the
functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations. When
the control word is read, bit D7 will always be a logic “1”, as this
implies control word mode information.
Ports A, B, and C
The 82C55A contains three 8-bit ports (A, B, and C). All can be
configured to a wide variety of functional characteristics by the
system software but each has its own special features or
“personality” to further enhance the power and flexibility of the
82C55A.
Port A
One 8-bit data output latch/buffer and one 8-bit data
input latch.
Port B
One 8-bit data input/output latch/buffer and one 8-bit
data input buffer.
Port C
One 8-bit data output latch/buffer and one 8-bit data input
buffer (no latch for input). This port can be divided into two 4-bit
ports under the mode control. Each 4-bit port contains a 4-bit
latch and it can be used for the control signal output and status
signal inputs in conjunction with ports A and B.
(RESET)
Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input mode.
FN6140 Rev 2.00
June 15, 2006
Page 4 of 26
MS82C55A, MQ82C55A, MP82C55A
Operational Description
Mode Selection
There are three basic modes of operation than can be selected
by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
When the reset input goes “high”, all ports will be set to the
input mode. After the reset is removed, the 82C55A can
remain in the input mode with no additional initialization
required. The control word register will contain 9Bh. During the
execution of the system program, any of the other modes may
be selected using a single output instruction. This allows a
single 82C55A to service a variety of peripheral devices with a
simple software maintenance routine. Any port programmed as
an output port is initialized to all zeros when the control word is
written.
ADDRESS BUS
CONTROL BUS
DATA BUS
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
RD, WR
D7-D0
82C55A
MODE 0
B
8
I/O
4
C
A0-A1
CS
A
4
I/O
8
I/O
I/O
PB7-PB0
MODE 1
B
8
I/O
PC3-PC0
C
PC7-PC4
PA7-PA0
A
8
I/O
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the Port
A and Port B definitions. All of the output registers, including
the status flip-flops, will be reset whenever the mode is
changed. Modes may be combined so that their functional
definition can be “tailored” to almost any I/O structure. For
instance: Group B can be programmed in Mode 0 to monitor
simple switch closings or display computational results, Group
A could be programmed in Mode 1 to monitor a keyboard or
tape reader on an interrupt-driven basis.
The mode definitions and possible mode combinations may seem
confusing at first, but after a cursory review of the complete device
operation a simple, logical I/O approach will surface. The design
of the 82C55A has taken into account things such as efficient PC
board layout, control signal definition vs. PC layout and complete
functional flexibility to support almost any peripheral device with
no external logic. Such design represents the maximum use of
the available pins.
PB7-PB0
MODE 2
CONTROL CONTROL
OR I/O
OR I/O
C
PA7-PA0
B
8
I/O
A
BI-
DIRECTIONAL
PB7-PB0
CONTROL
PA7-PA0
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
FN6140 Rev 2.00
June 15, 2006
Page 5 of 26
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