DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD23C64040BL
64M-BIT MASK-PROGRAMMABLE ROM
8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Description
The
µ
PD23C64040BL is a 67,108,864 bits mask-programmable ROM. The word organization is selectable (BYTE
mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
µ
PD23C64040BL is packed in 48-pin PLASTIC TSOP (I).
Features
•
Word organization
8,388,608 words by 8 bits (BYTE mode)
4,194,304 words by 16 bits (WORD mode)
•
Page access mode
BYTE mode : 8 byte random page access
WORD mode : 4 word random page access
•
Operating supply voltage : V
CC
= 2.7 to 3.6 V
Operating supply voltage Access time / Page access time Power supply current (Active mode) Standby current (CMOS level input)
V
CC
3.3 V
±
0.3 V
3.0 V
±
0.3 V
ns (MAX.)
90 / 25
100 / 25
mA (MAX.)
65
55
µ
A (MAX.)
30
30
Ordering Information
Part number
Package
48-pin PLASTIC TSOP (I) (12
×
18) (Normal bent)
48-pin PLASTIC TSOP (I) (12
×
18) (Reverse bent)
µ
PD23C64040BLGY-xxx-MJH
µ
PD23C64040BLGY-xxx-MKH
(xxx : ROM code suffix No.)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15277EJ2V0DS00 (2nd edition)
Date Published July 2001 NS CP (K)
Printed in Japan
©
2001
µ
PD23C64040BL
Pin Configurations (Marking Side)
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12
×
18) (Normal bent)
[
µ
PD23C64040BLGY-xxx-MJH ]
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
V
CC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE, OE, DC
GND
GND
A0 - A21
O0 - O7, O8 - O14
O15, A−1
WORD, /BYTE
/CE
/OE, OE
V
CC
GND
NC
DC
Note
: Address inputs
: Data outputs
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
: Chip Enable
: Output Enable
: Supply voltage
: Ground
: No Connection
: Don’t Care
Note
Some signals can be applied because this pin is not connected to the inside of the chip.
Remark
Refer to
Package Drawings
for the 1-pin index mark.
2
Data Sheet M15277EJ2V0DS
µ
PD23C64040BL
48-pin PLASTIC TSOP (I) (12
×
18) (Reverse bent)
[
µ
PD23C64040BLGY-xxx-MKH ]
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
V
CC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE, OE, DC
GND
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
A0 - A21
O0 - O7, O8 - O14
O15, A−1
WORD, /BYTE
/CE
/OE, OE
V
CC
GND
NC
DC
Note
: Address inputs
: Data outputs
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
: Chip Enable
: Output Enable
: Supply voltage
: Ground
: No Connection
: Don’t Care
Note
Some signals can be applied because this pin is not connected to the inside of the chip.
Remark
Refer to
Package Drawings
for the 1-pin index mark.
Data Sheet M15277EJ2V0DS
3
µ
PD23C64040BL
Input / Output Pin Functions
Pin name
WORD, /BYTE
Input / Output
Input
Function
The pin for switching WORD mode and BYTE mode.
High level
: WORD mode (4M-word by 16-bit)
Low level
: BYTE mode (8M-word by 8-bit)
Address input pins.
A0 to A21 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
A0 to A21 are used as 22 bits address signals.
BYTE mode (8M-word by 8-bit)
A0 to A21 are used as the upper 22 bits of total 23 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE
mode.
WORD mode (4M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (8M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (8M-word by 8-bit)
The least significant address bus (A−1).
Chip activating signal.
When the OE is active, output states are following.
High level:
High impedance
Low level
: Data out
Output enable signal. The active level of OE is mask option. The active level
of OE can be selected from high active, low active and Don’t care at order.
Supply voltage
Ground
Not internally connected (The signal can be connected).
A0 to A21
(Address inputs)
Input
O0 to O7, O8 to O14
(Data outputs)
Output
O15, A−1
(Data output 15,
LSB Address input)
Output, Input
/CE
(Chip Enable)
Input
/OE, OE, DC
(Output Enable, Don't Care)
V
CC
GND
NC
Input
–
–
–
4
Data Sheet M15277EJ2V0DS
µ
PD23C64040BL
Block Diagram
O8
O0
O1
O9
O2
O10
O11
O3
O12
O4
O5
O13
O6
O14
O15, A–1
O7
A0
A1
A2
A3
A4
A5
A6
A7
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A8
Output Buffer
Y-Decoder
Logic/Input
WORD, /BYTE
/OE, OE, DC
Y-Selector
Address Input Buffer
Memory Cell Matrix
X-Decoder
Input Buffer
4,194,304 words by 16 bits /
8,388,608 words by 8 bits
/CE
Data Sheet M15277EJ2V0DS
5
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