ADVANCE
‡
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
FLASH AND CellularRAM
™
COMBO MEMORY
Features
• Stacked die Combo package
Includes two 64Mb Flash devices
Choice of either one 32Mb or one 64Mb
CellularRAMÔ device
• Basic configuration
Flash
Flexible multibank architecture
4 Meg x 16 Async/Page/Burst interface
Support for true concurrent operations with
no latency
CellularRAM
Low-power, high-density design
2 Meg x 16 or 4 Meg x 16 configurations
Async/Page
• F_V
CC
, V
CC
Q, F_V
PP
, PS_V
CC
voltages
1.70V (MIN)/1.95V (MAX) F_V
CC
, PS_V
CC
1.70V (MIN)/2.24V (MAX) V
CC
Q (W18)
1.70V (MIN)/3.3V(MAX) V
CC
Q (W30)
1.80V (TYP) F_V
PP
(in-system PROGRAM/ERASE)
12V ±5% (HV) F_V
PP
(in-house programming and
accelerated programming algorithm [APA]
activation)
• Asynchronous access time
Flash/CellularRAM access time: 60ns @ 1.70V V
CC
• Page Mode read access (W18/W30)
Interpage read access: 60ns @ 1.70V F_V
CC
, PS_V
CC
(W18)
Intrapage read access: 20ns @ 1.70V F_V
CC
, PS_V
CC
(W18)
Interpage read access: 70ns @ 1.70V F_VCC , PS_VCC (W30)
Intrapage read access: 22ns @ 1.70V F_VCC, PS_VCC (W30)
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write CellularRAM during program/erase of
Flash
• Each Flash contains two 64-bit chip protection
registers for security purposes
• Flash PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
Extended command set
Common Flash interface (CFI) compliant
• Manufacturer’s ID (ManID)
Micron
®
(0x2Ch)
Intel
®
(0x89h)
MT28C128532W18/W30D
MT28C128564W18/W30D
Low Voltage, Wireless Temperature
Figure 1: 77-Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
A4
2
A18
3
A19
4
PS_V
SS
5
F_V
CC
6
F_V
CC
7
A21
8
A11
A5
PS_LB#
PS_V
SS
NC
CLK
NC
A12
A3
A17
F_V
PP
PS_WE#
PS_CE#
A9
A13
A2
A7
F_WP#
ADV#
A20
A10
A15
A1
A6
PS_UB# F_RST#
F_WE#
A8
A14
A16
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT#
F_CE2#
PS_OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F_OE2#
NC
F_OE1#
DQ9
DQ11
DQ4
DQ6
DQ15
V
CC
Q
F_CE1#
NC
NC
NC
PS_V
CC
F_V
CC
V
CC
Q
PS_ZZ#
PS_V
SS
V
SS
Q
V
CC
Q
F_V
CC
PS_V
SS
V
SS
Q
F_V
SS
PS_V
SS
Top View
(Ball Down)
O
ptions
• Timing
60ns
70ns
• Burst Frequency
66 MHz
1
54 MHz
• Boot Block Configuration
Top/Top
Top/Bottom
Bottom/Top
Bottom/Bottom
• I/O Voltage Range
VccQ 1.70V–1.95V
VccQ 1.70V–3.3V
• Manufacturer’s ID (ManID)
Micron (0x2Ch)
Intel (0x89h)
• Operating Temperature Range
Wireless Temperature (-25°C to +85°C)
• Package
77-ball FBGA (8 x 10 grid)
NOTE:
1. Contact factory for availability.
Part Number Example:
M
arking
-60
-70
6
5
TT
TB
BT
BB
18
30
None
K
WT
FW
MT28C128564W18DFW-705 BBWT
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
1
©2003 Micron Technology, Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MultiChip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Unique IDs, State Machines, and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Flash Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Flash Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
ADVANCE
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
ADVANCE
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Cross-Reference for Abbreviated Device Marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Possible Boot Configurations for Flash Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
ADVANCE
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
General Description
The
MT28C128532W18/W30D
and
MT28C128564W18/W30D combination Flash and Cel-
lularRAM are high-performance, high-density, mem-
ory solutions that can significantly improve system
performance. The Flash architecture features a multi-
partition configuration that supports READ-while-
PROGRAM/ERASE operations with no latency. A 4Mb
partition size enables optimal design flexibility.
Two Flash devices are stacked to achieve the 128Mb
density. Each Flash die has a dedicated CE# and OE#
control, enabling each Flash to be independently select-
able.
The
MT28C128532W18/W30D
and
MT28C128564W18/W30D stacked Flash devices
enable soft protection for blocks, as read only, by con-
figuring soft protection registers with dedicated com-
mand sequences. For security purposes, two user-
programmable 64-bit chip protection registers are pro-
vided for each Flash device.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
Each Flash device has a read configuration register
(RCR) that defines how the Flash interacts with the mem-
ory bus. For device specifications and additional docu-
mentation concerning Flash and CellularRAM features,
please refer to the MT28F644W18/W30 data sheet at
www.micron.com/flash
and the MT45W2MW16PFA and
MT45W4MW16PFA
data
sheets
at
http://
www.micron.com/cellularram.
The CellularRAM architecture features high-speed
CMOS, dynamic random-access memories developed
for low-power portable applications The CellularRAM
device is available in either 32Mb or 64Mb densities.
To operate seamlessly on a burst Flash bus, Cellular-
RAM products have incorporated a transparent self-
refresh mechanism. The hidden refresh requires no
additional support from the system memory controller
and has no significant impact on device read/write per-
formance.
The refresh configuration register (CR) is used to con-
trol how refresh is performed on the DRAM array. These
registers are automatically loaded with default settings
during power-up and can be updated any time during
normal operation. Special attention has been focused
on standby current consumption during self-refresh.
CellularRAM products include three system-acces-
sible mechanisms used to minimize standby current.
Partial array refresh (PAR) limits refresh to the portion
of the memory array being used. Temperature com-
pensated refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower temperatures to
minimize current consumption during standby. Deep
power down (DPD) halts the REFRESH operation alto-
gether and is used when no vital information is stored
in the device. These three refresh mechanisms are
adjusted through the CR.
Please refer to Micron’s Web site
www.micron.com/
flash
for the latest MT28F644W18/W30 Flash data
sheet and
http://www.micron.com/cellularram
for the
latest MT45W2MW16PFA and MT45W4MW16PFA Cel-
lularRAM data sheet.
Flash Configurations
Each Flash memory implements a multibank archi-
tecture (16 banks of 4Mb each) to allow concurrent
operations. Any address within a block address range
selects that block for the required READ, PROGRAM, or
ERASE operation.
Each Flash memory features eight 4K-word sectors
(8 x 65,536 bits), designated as parameter blocks, and
the remaining part is organized in main blocks of 32K
words each (524,288 bits). The parameter blocks are
addressed either by the low order addresses (bottom
boot) or by the higher order addresses (top boot).
The two Flash devices can be supplied with any
combination of top or bottom boot (e.g., top/top, bot-
tom/bottom, top/bottom, or bottom/top). Please see
Figures 2 and 3 for more information.
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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