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SM364TCSMB3II15

产品描述Cache Tag SRAM Module, 32KX64, CMOS, DIMM-160
产品类别存储    存储   
文件大小30KB,共5页
制造商SMART Modular Technology Inc
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SM364TCSMB3II15概述

Cache Tag SRAM Module, 32KX64, CMOS, DIMM-160

SM364TCSMB3II15规格参数

参数名称属性值
厂商名称SMART Modular Technology Inc
零件包装代码DIMM
包装说明,
针数160
Reach Compliance Codeunknown
ECCN代码3A991.B.2.A
其他特性8K X 8 TAG
JESD-30 代码R-XDMA-N160
内存密度2097152 bit
内存集成电路类型CACHE TAG SRAM MODULE
内存宽度64
功能数量1
端子数量160
字数32768 words
字数代码32000
工作模式SYNCHRONOUS
组织32KX64
封装主体材料UNSPECIFIED
封装形状RECTANGULAR
封装形式MICROELECTRONIC ASSEMBLY
并行/串行PARALLEL
认证状态Not Qualified
最大供电电压 (Vsup)3.63 V
最小供电电压 (Vsup)2.97 V
标称供电电压 (Vsup)3.3 V
表面贴装NO
技术CMOS
端子形式NO LEAD
端子位置DUAL

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SM364TCSMB3UI15
Modular Technologies
SMART
February 1997
Rev 0
SM364TCSMB3UI15
256KByte (32Kx64) Synchronous Secondary Cache SRAM Module
General Description
The SM364TCSMB3UI15 is a high performance, 256
Kilobyte synchronous secondary cache SRAM module for
use with Intel Triton Chipset. It is organized as 32K
words by 64 bits, in a 160-pin, dual readout, leadless,
double-in-line memory module (DIMM) package.
The module utilizes two CMOS 32Kx32 static RAMs for
data and two 8Kx8 static RAM for tag in surface mount
packages on an epoxy laminate substrate. Each device is
accompanied by decoupling capacitors for improved noise
immunity.
Control lines provided are such that byte write control is
possible.
Functional Diagram
CWE4#~CWE7#
CWE0#~CWE3#
CADS#
ADSP#
CADV#
CCS#
COE#
BWE#
GWE#
CLK0
VCC3
ECS1#, ECS2#
A3
A4
A5~A17
MODE
BW1#~BW4#
ADSC#
ADSP#
ADV#
CS#
OE#
BWE#
GWE#
CLK
32Kx32
CS2
SRAM
CS2#
A0
A1
A2~A14
MODE
D0~D31
BW1#~BW4#
ADSC#
ADSP#
ADV#
CS#
OE#
BWE#
GWE#
CLK
32Kx32
CS2
SRAM
CS2#
A0
A1
A2~A14
MODE
D32~D63
Features
COASt 3.1 compliant
High Density : 256KByte
Fast Cycle Time of 15ns (max.)
Low Power (typical) :
Active :
3.1W
Standby :
440mW - TTL/LVTTL
220W - CMOS
TTL-compatible inputs and outputs
Separate power and ground planes
Dual power supplies : 5V+10%
3.3V±10%
Height : 1.250"
DATA RAMs
D0~D63
A0~A12
A0~A12
TAG RAMs
8Kx8
8Kx8
TWE#
WE# SRAM
WE# SRAM
ECS1#, ECS2#
CE1#
CE1#
Notes:
1. All the data lines are terminated using
(Data RAMs)
V
CC3
V
SS
series resistors.
TIO0~TIO7
TIO8~TIO10
2. MODE has a pull-up resistor of 4.7KΩ.
3. TIO8, TIO9 have pull-up resistors and TIO10
(Tag RAMs)
V
CC5
V
SS
TIO0~TIO10
has a pull-down resistor of 8.2KΩ.
4. All unused tag bits have pull-down resistors of
Decoupling capacitors
150KΩ.
to all devices
(All specifications of this device are subject to change without notice.)
Corporate Headquarters:
4305 Cushing Pkwy., Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: + 44-1908 234030 • Fax: + 44-1908-234191
Asia/Pacific:
Suite 6A, 64 Canning Hwy., Victoria Park, Perth, WA 6106, Australia • Tel: + 61-9-361-9705 • Fax: + 61-9-361-9715
1

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