HY57V283220T-I/ HY5V22F-I
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V283220T-I / HY5V22F-I is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the mem-
ory applications which require wide data I/O and high bandwidth. HY57V283220T-I / HY5V22F-I is organized as
4banks of 1,048,576x32.
HY57V283220T-I / HY5V22F-I is offering fully synchronous operation referenced to a positive edge of the clock. All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to
achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
•
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
•
•
Internal four banks operation
•
Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
ORDERING INFORMATION
Part No.
HY57V283220(L)T-5I
HY5V22(L)F-5I
HY57V283220(L)T-55I
HY5V22(L)F-55I
HY57V283220(L)T-6I
HY5V22(L)F-6I
HY57V283220(L)T-7I
HY5V22(L)F-7I
HY57V283220(L)T-8I
HY5V22(L)F-8I
HY57V283220(L)T-PI
HY5V22(L)F-PI
HY57V283220(L)T-SI
HY5V22(L)F-SI
Clock Frequency
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
100MHz
Organization
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
Interface
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Package
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6/Nov. 02
HY57V283220T-I / HY5V22F-I
PIN CONFIGURATION ( HY57V283220T-I Series)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DD
DQM0
/W E
/C A S
/R A S
/C S
A11
BA0
BA1
A 1 0 /A P
A0
A1
A2
DQM2
V
DD
NC
D Q 16
V
SSQ
D Q 17
D Q 18
V
DDQ
D Q 19
D Q 20
V
SSQ
D Q 21
D Q 22
V
DDQ
D Q 23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
D Q 15
V
SSQ
D Q 14
D Q 13
V
DDQ
D Q 12
D Q 11
V
SSQ
D Q 10
DQ9
V
DDQ
DQ8
NC
V
SS
DQM1
NC
NC
C LK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
D Q 31
V
DDQ
D Q 30
D Q 29
V
SSQ
D Q 28
D Q 27
V
DDQ
D Q 26
D Q 25
V
SSQ
D Q 24
V
SS
8 6 p in T S O P I I
4 0 0 m il x 8 7 5 m il
0 . 5 m m p in p i t c h
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.6/Nov. 02
2
HY57V283220T-I / HY5V22F-I
Ball CONFIGURATION ( HY5V22F-ISeries)
1
A
D Q 26
DQ 24
VSS
VDD
DQ 23
D Q 21
2
3
4
5
6
7
8
9
B
D Q 28
VDDQ
VSSQ
VDDQ
VSSQ
D Q 19
C
VSSQ
DQ 27
D Q 25
D Q 22
DQ 20
VDDQ
D
VSSQ
DQ 29
D Q 30
D Q 17
DQ 18
VDDQ
E
VDDQ
DQ 31
NC
NC
DQ 16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
T o p V ie w
NC
BA1
A 11
J
C LK
CKE
A9
BA0
/C S
/R A S
K
DQM1
NC
NC
/C A S
/W E
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
D Q 10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
D Q 12
DQ 14
DQ1
DQ3
VDDQ
P
DQ 11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
DQ 13
D Q 15
VSS
VDD
DQ0
DQ2
Ball DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.6/Nov. 02
3
HY57V283220T-I / HY5V22F-I
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Row Active
1M x32 Bank 3
Row
Pre
Decoder
1M x32 Bank 2
X decoder
X decoder
X decoder
X decoder
X decoder
1M x32 Bank 1
1M x32 Bank 0
DQ0
DQ1
I/O Buffer & Logic
I/O Buffer & Logic
Sense AMP & I/O Gate
Sense AMP & I/O Gate
State Machine
State Machine
Column
Active
X decoder
Memory
Cell
Array
Column
Pre
Decoder
Y decoder
DQ30
DQ31
Bank Select
Column Add
Counter
A0
A1
Address buffers
Address buffers
A11
BA0
BA1
Address
Register
Burst
Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.6/Nov. 02
4
HY57V283220T-I / HY5V22F-I
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
-40 ~ 85
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA=-40 to 85°C)
Parameter
Power Supply Voltage
Input high voltage
Input low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.135
2.0
V
SSQ
- 0.3
Typ.
3.3
3.0
0
Max
3.6
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1
1,2
1,3
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with
≤3ns
of duration with no input clamp diodes
3.V
IL
(min) is acceptable -2.0V AC pulse width with
≤3ns
of duration with no input clamp diodes
AC OPERATING CONDITION
(TA=-40 to 85°C, 3.0V
≤V
DD
≤3.6V,
V
SS
=0V - Note1)
Parameter
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
CL
Value
2.4/0.4
1.4
1
1.4
30
Unit
V
V
ns
V
pF
1
Note
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.6/Nov. 02
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
