TECHNOLOGY, INC.
1 MEG x 16
FPM DRAM
MT4C1M16C3
MT4LC1M16C3
DRAM
FEATURES
• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
• High-performance, low power CMOS silicon-gate
process
• Single power supply (+3.3V
±0.3V
or 5V
±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Optional Self Refresh (S) for low power data retention
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View)
42-Pin SOJ
(DA-7)
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
Vss
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
44/50-Pin TSOP
(DB-6)
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
OPTIONS
• Voltage
3.3V
5V
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
• Timing
60ns access
70ns access (3.3V only)
• Refresh Rate
Standard 16ms period
Self Refresh and 128ms period
MARKING
LC
C
DJ
TG
-6
-7
None
S
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
Vcc
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
Vss
Note:
The # symbol indicates signal is active LOW.
1 MEG x 16 FPM DRAM PART NUMBERS
PART NUMBER
MT4LC1M16C3DJ
MT4LC1M16C3DJS
MT4LC1M16C3TG
MT4LC1M16C3TGS
MT4C1M16C3DJ
MT4C1M16C3DJS
MT4C1M16C3TG
MT4C1M16C3TGS
V
CC
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
• Part Number Example: MT4LC1M16C3TG-6
Note: The 1 Meg x 16 FPM DRAM base number differentiates the offerings in
one place -
MT4LC1M16C3.
The third field distinguishes the low voltage
offering: LC designates Vcc = 3.3V and C designates Vcc = 5V.
KEY TIMING PARAMETERS
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
130ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
GENERAL DESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x16 con-
figuration. The 1 Meg x 16 DRAM has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
1 Meg x 16 FPM DRAM
D51.pm5 – Rev. 3/97
(CASL# and CASH#). These function in an identical man-
ner to a single CAS# of other DRAMs in that either CASL#
or CASH# will generate an internal CAS#.
The CAS# function and timing are determined by the first
CAS# (CASL# or CASH#) to transition LOW and the last
CAS# to transition back HIGH. Use of only one of the two
results in a BYTE access cycle. CASL# transitioning LOW
selects an access cycle for the lower byte (DQ1-DQ8) and
CASH# transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
FPM DRAM
GENERAL DESCRIPTION (continued)
Each bit is uniquely addressed through the 20 address
bits during READ or WRITE cycles. These are entered 10
bits (A0 -A9) at a time. RAS# is used to latch the first 10 bits
and CAS# the latter 10 bits. The CAS# function is deter-
mined by the first CAS# (CASL# or CASH#) to transition
LOW and the last one to transition back HIGH. The CAS#
function also determines whether the cycle will be a refresh
cycle (RAS#-ONLY) or an active cycle (READ, WRITE or
READ WRITE) once RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal functioning in an identical manner to the
single CAS# input of other DRAMs. The key difference is
each CAS# input (CASL# and CASH#) controls its corre-
sponding DQ tristate logic (in conjunction with OE# and
WE#). CASL# controls DQ1 through DQ8 and CASH#
controls DQ9 through DQ16. The two CAS# controls give
the 1 Meg x 16 DRAM BYTE WRITE cycle capabilities.
A logic HIGH on WE# dictates READ mode while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS, whichever occurs last. Taking WE# LOW will initiate
WORD WRITE
RAS#
a WRITE cycle, selecting DQ1 through DQ16. If WE# goes
LOW prior to CAS# going LOW, the output pin(s) remain
open (High-Z) until the next CAS# cycle. If WE# goes LOW
after CAS# goes LOW and data reaches the output pins,
data-out (Q) is activated and retains the selected cell data as
long as CAS# and OE# remain LOW (regardless of WE# or
RAS#). This late WE# pulse results in a READ WRITE cycle.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
OE# and WE#.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (A0 -A9) page boundary. The FAST
PAGE MODE cycle is always initiated with a row address
strobed-in by RAS# followed by a column address strobed-
in by CAS#. CAS# may be toggled-in by holding RAS#
LOW and strobing-in different column addresses, thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST PAGE MODE operation.
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE
(DQ1-DQ8)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED STORED
DATA
DATA
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
UPPER BYTE
(DQ9-DQ16)
OF WORD
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
ADDRESS 1
1
0
1
0
1
1
1
1
ADDRESS 0
X = NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD AND BYTE WRITE EXAMPLE
1 Meg x 16 FPM DRAM
D51.pm5 – Rev. 3/97
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
FPM DRAM
FAST PAGE MODE
(continued)
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby
level. The chip is also preconditioned for the next cycle
during the RAS# HIGH time. Memory cell data is retained
in its correct state by maintaining power and executing any
RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#
ONLY, CBR, or HIDDEN) so that all 1,024 combinations of
RAS# addresses (A0 -A9) are executed at least every 16ms
(128ms on the “S” version), regardless of sequence. The
CBR Refresh cycle will also invoke the refresh counter and
controller for row-address control.
select an upper BYTE access (DQ9-DQ16). Enabling both
CASL# and CASH# selects a WORD WRITE cycle.
The 1 Meg x 16 DRAM may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the excep-
tion of the CAS# inputs. Figure 1 illustrates the BYTE WRITE
and WORD WRITE cycles. Figure 2 illustrates BYTE READ
and WORD READ cycles.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS# precharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes. For example, an EARLY
WRITE on one byte and a LATE WRITE on the other byte
are not allowed during the same cycle. However, an EARLY
WRITE on one byte and, after a CAS# precharge has been
satisfied, a LATE WRITE on the other byte are permissible.
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by
the use of CASL# and CASH#. Enabling CASL# will select
a lower BYTE access (DQ1-DQ8). Enabling CASH# will
WORD READ
RAS#
LOWER BYTE READ
CASL#
CASH#
WE#
STORED
DATA
1
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED STORED
DATA
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
LOWER BYTE
(DQ1-DQ8)
OF WORD
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
UPPER BYTE
(DQ9-DQ16)
OF WORD
ADDRESS 0
Z = High-Z
ADDRESS 1
Figure 2
WORD READ EXAMPLE
1 Meg x 16 FPM DRAM
D51.pm5 – Rev. 3/97
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
FPM DRAM
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR, or HIDDEN) so that all
1,024 combinations of RAS# addresses are executed within
t
REF (MAX), regardless of sequence. The CBR and Ex-
tended and Self Refresh cycles will invoke the internal
refresh counter for automatic RAS# addressing.
The optional Self Refresh mode is available on the “S”
version. The “S” option allows the user a dynamic refresh,
data retention mode at the extended refresh period of
128ms, i.e. 125µs per row when using distributed CBR
refreshes. The “S” option also allows the user the choice of
a fully static low-power data retention mode. The optional
Self Refresh feature is initiated by performing a CBR Re-
fresh cycle and holding RAS# LOW for the specified
t
RASS.
The Self Refresh mode is terminated by driving
RAS# HIGH for a minimum time of
t
RPS. This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS# LOW-to-HIGH transi-
tion. If the DRAM controller uses a distributed refresh
sequence, a burst refresh is not required upon exiting Self
Refresh. However, if the DRAM controller utilizes RAS#-
ONLY or burst refresh sequence, all 1,024 rows must be
refreshed within the average internal refresh rate prior to
the resumption of normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
FUNCTIONAL BLOCK DIAGRAM
WE#
CASL#
CASH#
DQ1
16
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
10
CAS#
DATA-IN BUFFER
DQ16
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLLER
COLUMN
DECODER
16
1024
OE#
16
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
10
ROW
ADDRESS
BUFFERS (10)
ROW
DECODER
1024 x 16
10
1024
1024 x 1024 x 16
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
Vcc
Vss
1 Meg x 16 FPM DRAM
D51.pm5 – Rev. 3/97
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
FPM DRAM
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ: WORD
READ: LOWER BYTE
READ: UPPER BYTE
WRITE: WORD
(EARLY WRITE)
WRITE: LOWER
BYTE (EARLY)
WRITE: UPPER
BYTE (EARLY)
READ WRITE
PAGE-MODE
READ
PAGE-MODE
WRITE
PAGE-MODE
HIDDEN
REFRESH
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
READ
WRITE
RAS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
H→L
CASL#
H→X
L
L
H
L
L
H
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
L
CASH#
H→X
L
H
L
L
H
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
L
WE#
X
H
H
H
L
L
L
H→L
H
H
L
L
H→L
H→L
H
L
X
H
H
OE#
X
L
L
L
X
X
X
L→H
L
L
X
X
L→H
L→H
L
X
X
X
X
t
R
t
C
DQs
High-Z
Data-Out
Lower Byte, Data-Out
Upper Byte, Data-Out
Lower Byte, Data-Out
Upper Byte, Data-Out
Data-In
Lower Byte, Data-In
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out, Data-In
Data-Out, Data-In
Data-Out
Data-In
High-Z
High-Z
High-Z
NOTES
X
ROW
ROW
ROW
ROW
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
X
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
X
X
1
1
1
1
1
1, 2
3
3
READ-WRITE 2nd Cycle
RAS#-ONLY REFRESH
CBR REFRESH
SELF REFRESH
NOTE:
1. These WRITE cycles may also be BYTE WRITE cycles (either CASL# or CASH# active).
2. EARLY WRITE only.
3. Only one CAS# must be active (CASL# or CASH#).
1 Meg x 16 FPM DRAM
D51.pm5 – Rev. 3/97
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
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