MB84VZ064D
-70
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices
and Fujitsu. Although the document is marked with the name of the company that originally developed the specifi-
cation, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal datasheet improvement and are noted in the document revision summary,
where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision sum-
mary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these prod-
ucts, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number
26829
Revision
A
Amendment
0
Issue Date
October 25, 2002
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50501-1E
4 Stacked MCP (Multi-Chip Package) FLASH & FLASH & FCRAM & SRAM
CMOS
64M (×16) FLASH MEMORY &
64M (×16) FLASH MEMORY &
32M (×16) Mobile FCRAM
TM
&
8M (×16) STATIC RAM
MB84VZ064D-70
s
FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V
• High Performance
70 ns maximum access time (Flash_1or Flash_2)
70 ns maximum access time (FCRAM)
70 ns maximum access time (SRAM)
• Operating Temperature
–30
°C
to +85
°C
• Package 107-ball FBGA
(Continued)
s
PRODUCT LINEUP
Flash_1 or Flash_2
Supply Voltage (V)
Max Address Access Time
(ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
f_1*/V
CC
f_2* = 3.0 V
70
70
30
+0.1V
–0.3 V
FCRAM
V
CC
r* = 3.0 V
70
70
40
+0.1V
–0.3 V
SRAM
V
CC
s* = 3.0 V
70
70
35
+0.1V
–0.3 V
* : All of V
CC
f_1, V
CC
f_2, V
CC
r and V
CC
s must be the same level when either part is being accessed.
s
PACKAGE
107-ball plastic FBGA
BGA-107P-M01
MB84VZ064D-70
1. FLASH MEMORY_1 and FLASH MEMORY_2
•
Simultaneous Read/Write Operations
(Dual
Bank)
•
FlexBank
TM
*
1
Bank A : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Bank B : 24 Mbit (64 KB
×
48)
Bank C : 24 Mbit (64 KB
×
48)
Bank D : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Two virtual Banks are chosen from the combination of four physical banks.
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
• Minimum 100,000 Program/Erase Cycles
•
Sector Erase Architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
•
HiddenROM
(HiddenROM)
Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC Input Pin
At V
IL
, allows protection of “outermost” 2
×
8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
•
Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
•
Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
•
Ready/Busy Output
(RY/BY_1
or RY/BY_2)
Hardware method for detection of program or erase cycle completion
•
Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode.
•
Low V
CC
f write Inhibit
≤
2.5 V
•
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
•
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Please Refer to “MBM29DL64DF” Datasheet in Detailed Function.
(Continued)
2
MB84VZ064D-70
(Continued)
2. FCRAM
TM
*
3
• Power Dissipation
Operating : 25 mA Max
Standby
: 100
µA
Max
• Power Down Mode
Sleep
: 10
µA
Max
NAP
: 60
µA
Max
8M Partial : 70
µA
Max
• Power Down Control by CE2r
• Byte Write Control: LB(DQ
7
-DQ
0
), UB(DQ
15
-DQ
8
)
• 8 words Address Access Capability
3. SRAM
• Power Dissipation
Operating : 50 mA Max
Standby : 15
µA
Max
• Power Down Features using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.1 V
• CE1s and CE2s Chip Select
• Byte Data Control: LB (DQ
7
-DQ
0
), UB (DQ
15
-DQ
8
)
*1: FlexBank
TM
is a trademark of Fujitsu Limited, Japan.
*2: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
*3: FCRAM
TM
is a trademark of Fujitsu Limited, Japan.
3
MB84VZ064D-70
s
PIN ASSIGNMENT
(Top View)
Marking Side
A10
N.C.
A9
N.C.
B10
N.C.
B9
N.C.
B8
N.C.
B7
N.C.
B6
N.C.
B5
CEf_2
B4
RY/BY_2
B3
VSS
C10
N.C.
C9
N.C.
C8
A11
C7
A8
C6
WE
C5
D10
N.C.
D9
A15
D8
A12
D7
A19
D6
CE2r
D5
E10
N.C.
E9
A21
E8
A13
E7
A9
E6
A20
E5
F10
N.C.
F9
N.C.
F8
A14
F7
A10
F6
N.C.
F5
CE1s
F4
A17
F3
A4
F2
A1
F1
N.C.
G10
N.C.
G9
A16
G8
PE
G7
DQ6
G6
CE2s
G5
VCCs
G4
DQ1
G3
VSS
G2
A0
G1
N.C.
H10
N.C.
H9
VCCf_1
H8
DQ15
H7
DQ13
H6
DQ4
H5
DQ3
H4
DQ9
H3
OE
H2
CEf_1
H1
N.C.
J10
N.C.
J9
VSS
J8
DQ7
J7
DQ12
J6
VCCr
J5
VCCf_1
J4
DQ10
J3
DQ0
J2
CE1r
J1
N.C.
K10
N.C.
K9
N.C.
K8
DQ14
K7
DQ5
K6
N.C.
K5
DQ11
K4
DQ2
K3
DQ8
K2
N.C.
K1
N.C.
L10
N.C.
L9
N.C.
L8
N.C.
L7
N.C.
L6
N.C.
L5
VCCf_2
L4
VSS
L3
RESET_2
L2
N.C.
L1
N.C.
M10
N.C.
M9
N.C.
WP/ACC RESET_1 RY/BY_1
C4
LB
C3
A7
C2
N.C.
C1
N.C.
D4
UB
D3
A6
D2
A3
D1
N.C.
E4
A18
E3
A5
E2
A2
E1
N.C.
A2
N.C.
A1
N.C.
B2
N.C.
M2
N.C.
M1
N.C.
(BGA-107P-M01)
4
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