152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Features
Mobile LPDDR (only)
152-Ball Package-on-Package (PoP) TI-OMAP™
MT46HxxxMxxLxCG
MT46HxxxMxxLxKZ
Features
• V
DD/
V
DDQ
= 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; 2 data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
per byte
• Programmable burst lengths (BLs): 2, 4, 8, or 16
1
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• STATUS REGISTER READ (SRR) supported
2
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh
Options
Marking
• V
DD/
V
DDQ
–
1.8V/1.8V
H
• Configuration
–
128 Meg x 32 (16 Meg x 16 x 4 banks x 4) 128M32
64M32
–
64 Meg x 32 (8 Meg x 32 x 4 banks x 2)
32M32
–
32 Meg x 32 (8 Meg x 32 x 4 banks)
16M32
–
16 Meg x 32 (4 Meg x 32 x 4 banks)
• Device version
–
Single die, standard addressing
LF
–
2-die stack, standard addressing
L2
–
4-die stack, standard addressing
L4
• Plastic “green” package
–
152-ball VFBGA (14 x 14 x 1.0mm)
CG
–
152-ball VFBGA (14 x 14 x 1.2mm)
KZ
• Timing – cycle time
–
5ns @ CL = 3
-5
–
5.4ns @ CL = 3
-54
-6
–
6ns @ CL = 3
• Operating temperature range
–
Commercial (0°C to +70°C)
None
–
Industrial (–40°C to +85°C)
IT
Notes: 1. BL 16: contact factory for availability.
2. Contact factory for remapped SRR output.
Table 1:
Architecture
Configuration
Configuration Addressing
128 Meg x 32
1
16 Meg x 16
x 4 banks x 4 die
8K
16K (A[13:0])
1K (A[9:0])
Notes:
64 Meg x 32
8 Meg x 32
x 4 banks x 2 die
8K
8K (A[12:0])
1K (A[9:0])
32 Meg x 32
8 Meg x 32
x 4 banks
8K
8K (A[12:0])
1K (A[9:0])
16 Meg x 32
4 Meg x 32
x 4 banks
8K
8K (A[12:0])
512 (A[8:0])
Refresh count
Row addressing
Column addressing
1. Quad die stack. Each CS configured with two x16 die connected in parallel to make up a 32-bit-
wide bus.
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Part Numbering Information – 152-Ball PoP
Part Numbering Information – 152-Ball PoP
Micron
®
152-ball packaged LPDDR devices are available in several configurations.
Figure 1:
Marketing Part Number Example
MT
Micron Technology
Product Family
46 = LPDDR-SDRAM
46
H 32M32 LF
CG
-6
IT
:A
Design Revision
:A = First generation
:B = Second generation
Operating Temperature
Operating Voltage
H = 1.8V/1.8V
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Configuration
128 Meg x 32
64 Meg x 32
32 Meg x 32
16 Meg x 32
Cycle Time
-5 = 5ns tCK CL = 3
-54 = 5.4ns tCK CL = 3
-6 = 6ns tCK CL = 3
Package Code
Device Version
LF = Single die, standard addressing
L2 = 2-die stack, standard addressing
L4 = Quad die, standard addressing
CG = 152-ball (14 x 14 x 1.0mm) VFBGA
KZ = 152-ball (14 x 14 x 1.2mm) VFBGA
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Device Marking
Table 2:
152-Ball Production Marketing Part Numbers
Part Numbers
MT46H16M32LFCG-5:B
MT46H16M32LFCG-5 IT:B
MT46H16M32LFCG-54:B
MT46H16M32LFCG-54 IT:B
MT46H16M32LFCG-6:B
MT46H16M32LFCG-6 IT:B
MT46H32M32LFCG-5:A
MT46H32M32LFCG-5 IT:A
MT46H32M32LFCG-54:A
MT46H32M32LFCG-54 IT:A
MT46H32M32LFCG-6:A
MT46H32M32LFCG-6 IT:A
MT46H64M32L2CG-5:A
MT46H64M32L2CG-5 IT:A
MT46H64M32L2CG-54:A
MT46H64M32L2CG-54 IT:A
MT46H64M32L2CG-6:A
MT46H64M32L2CG-6 IT:A
MT46H128M32L4KZ-6 IT ES:A
LPDDR Product
512Mb DDR, x32, 200 MHz
512Mb DDR, x32, 200 MHz
512Mb DDR, x32, 185 MHz
512Mb DDR, x32, 185 MHz
512Mb DDR, x32, 166 MHz
512Mb DDR, x32, 166 MHz
1Gb DDR, x32, 200 MHz
1Gb DDR, x32, 200 MHz
1Gb DDR, x32, 185 MHz
1Gb DDR, x32, 185 MHz
1Gb DDR, x32, 166 MHz
1Gb DDR, x32, 166 MHz
2 x 1Gb DDR, x32, 200 MHz
2 x 1Gb DDR, x32, 200 MHz
2 x 1Gb DDR, x32, 185 MHz
2 x 1Gb DDR, x32, 185 MHz
2 x 1Gb DDR, x32, 166 MHz
2 x 1Gb DDR, x32, 166 MHz
4 × 1Gb DDR, x32, 166 MHz
Physical Part Marking
D9KTK
D9KTL
D9KTM
D9KTN
D9KGX
D9KGZ
D9KTP
D9KLD
D9KTQ
D9KTR
D9KHL
D9JZJ
D9KTS
D9KLF
D9KTV
D9KTW
D9KJV
D9KFJ
Z9KZL
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu-
meric code is used. The abbreviated device marks are cross-referenced to the Micron
part numbers at the FBGA Part Marking Decoder site:
www.micron.com/decoder.
To
view the location of the abbreviated mark on the device, refer to customer service note
CSN-11, “Product Mark/Label,” at
www.micron.com/csn.
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
General Description
General Description
Micron 152-ball packaged Mobile Low-Power DDR SDRAM (LPDDR) devices contain
either 1Gb LPDDR or 512Mb LPDDR die.
The 1Gb LPDDR die is a high-speed CMOS, dynamic random-access memory
containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits.
The 512Mb LPDDR die is a high-speed CMOS, dynamic random-access memory
containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits.
Figure 2:
Functional Block Diagram
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
Command
decode
Control
logic
Bank 3
Bank 2
Refresh
counter
Bank 1
Standard mode
register
Extended mode
register
Bank 0
row-
address
latch
and
decoder
Row-
address
MUX
Bank 0
memory
array
32
64
Read
latch
MUX
32
DQS
generator
COL 0
32
Data
Sense amplifiers
DRVRS
4
DQ0–
DQ31
DQS
DQS0,
DQS1,
DQS2,
DQS3
RCVRS
32
32
Data
32
2
I/O gating
DM mask logic
Bank
control
logic
64
Mask
64
Write
FIFO
and
drivers
CK
out
CK
in
CK
4
4
8
32
64
Input
registers
4
Address,
BA0, BA1
Address
register
4
4
32
2
Column
decoder
Column-
address
counter/
latch
1
DM0,
DM1,
DM2,
DM3
CK
COL 0
4
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 3:
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
NC
NC
V
SSQ
DQ3
DQ0
V
SSQ
DQ4
DM0
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DNU
NC
1
2
NC
NC
DQS0
DQ5
DQ1
V
DDQ
DQ2
V
SS
NC
NC
NC
V
SS
NC
1
NC
V
SS
NC
1
NC
NC
NC
NC
NC
2
NC
NC
3
NC
NC
4
NC
NC
5
V
SS
NC
1
6
NC
1
V
SS
7
NC
NC
8
NC
NC
9
NC
NC
10
V
SS
V
DD
11
RFU
TQ
12
CKE1
V
SS
13
V
DD
V
DDQ
14
CKE0
A13
15
A10
V
SSQ
16
V
SS
V
DD
17
WE#
BA0
18
V
SSQ
V
DDQ
19
152-Ball VFBGA Ball Assignments
3
V
DDQ
DQ6
4
DM1
DQ7
5
DQ13
V
DDQ
6
DQ15
DQ9
7
V
SSQ
8
DQ10
9
10
11
DQ19
12
CK
13
V
SS
CK#
14
DM2
V
SSQ
15
V
DDQ
DQS2
16
DQ21
V
DD
17
DQ20
DQ23
18
DM3
19
DQS3
20
NC
NC
DQ24
DQ25
DQ27
V
SSQ
A0
V
SS
A2
A1
V
DDQ
A7
A8
V
SS
A5
CS1#
CAS#
BA1
V
SSQ
NC
NC
20
21
NC
NC
DQ26
DQ29
DQ31
V
DDQ
DQ30
V
DD
A3
A9
V
SSQ
A6
A11
V
DD
A12
CS0#
A4
RAS#
V
DDQ
DNU
NC
21
DQ12 DQ16
DQ8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
DQ14 DQS1 DQ11
DQ17 DQ18
DQ22 DQ28
Top View – Ball Down
LPDDR
Supply
Ground
Notes:
1. Although not bonded to the die, these pins may be connected on the package substrate.
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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