ADVANCE
‡
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDRIIb2 SRAM
18Mb
DDRII CIO SRAM
2-Word Burst
FEATURES
• 18Mb Density (2 Meg x 8, 1 Meg x 18, 512K x 36)
• DLL circuitry for wide-output, data valid window
and future frequency scaling
• Pipelined, double-data rate operation
• Common data input/output bus
• Fast clock to valid data times
• Full data coherency, providing most current data
• Two-tick burst for low DDR transaction size
• Permits up to one new data request per clock cycle
• Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• +1.8V core and HSTL I/O
• Clock-stop capability with
ms
restart
• 13 x 15mm, 1mm pitch, 11 x 15 grid FBGA package
• User programmable impedance output
• JTAG boundary scan
MT57W2MH8B
MT57W1MH18B
MT57W512H36B
165-BALL FBGA
GENERAL DESCRIPTION
The Micron® DDRII (Double Data Rate) synchro-
nous, pipelined, burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS pro-
cess. The DDR SRAM integrates an SRAM core with ad-
vanced synchronous peripheral circuitry and a burst
counter. All synchronous inputs pass through registers
controlled by an input clock pair (K and K#) and are
latched on the rising edge of K and K#. The synchronous
inputs include all addresses, all data inputs, active LOW
load (LD#), read/write (R/W#), and active LOW byte writes
or nybble writes (BWx# or NWx#). Write data is registered
on the rising edges of both K and K#. Read data is driven
on the rising edge of C and C# if provided, or on the rising
edge of K and K#, if C and C# are not provided.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical
pins as the data inputs D) are tightly matched to the
output data clocks C and C#, eliminating the need for
separately capturing data from each individual DDR
SRAM in the system design.
Additional write registers are incorporated to enhance
pipelined WRITE cycles and reduce READ-to-WRITE turn-
around time. WRITE cycles are self-timed.
OPTIONS
• Clock Cycle Timing
3ns (333 MHz)
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
2 Meg x 8
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
MARKING
-3
-3.3
-4
-5
-6
-7.5
MT57W2MH8B
MT57W1MH18B
MT57W512H36B
F
VALID PART NUMBERS
PART NUMBER
MT57W2MH8BF-xx
MT57W1MH18BF-xx
MT57W512H36BF-xx
DESCRIPTION
2 Meg x 8, DDRIIb2 FBGA
1 Meg x 18, DDRIIb2 FBGA
512K x 36, DDRIIb2 FBGA
18Mb 1.8V V
DD
, HSTL, DDRIIb2 SRAM
MT57W1MH18B_3.p65 – Rev. 3, Pub. 12/01
1
©2001, Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
‡
PRODUCTS
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDRIIb2 SRAM
GENERAL DESCRIPTION (continued)
Four pins are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test clock
(TCK), and test data-out (TDO). JTAG circuitry is used to
serially shift data to and from the SRAM. JTAG inputs use
1.8V I/O levels to shift data during this testing mode of
operation.
The device can be used in HSTL systems by supplying
an appropriate reference voltage (V
REF
). The device is
ideally suited for applications requiring very rapid data
transfer by operation in data-doubled mode. The device
is also ideal in applications requiring the cost benefits of
pipelined CMOS SRAMs and the reduced READ-to-WRITE
turnaround times of late write SRAMs.
The SRAM operates from a +1.8V power supply, and
all inputs and outputs are HSTL-compatible. The device
is ideally suited for cache, network, telecom, DSP, and
other applications that benefit from a very wide, high-
speed data bus.
Please refer to Micron’s Web site (www.micron.com/
sram)
for the latest data sheet.
DDR OPERATION
The DDR SRAM enables high performance operation
through high clock frequencies (achieved through pipe-
lining) and double data rate mode of operation. At slower
frequencies, the DDR SRAM requires a single NO OPERA-
TION (NOP) cycle when transitioning from a READ to a
WRITE cycle. At higher frequencies, a second NOP cycle
may be required to prevent bus contention. NOP cycles
are not required when switching from a WRITE to a
READ.
If a read occurs after a WRITE cycle, address and data
for the write are stored in registers. The write information
must be stored because the SRAM cannot perform the
last word write to the array without conflicting with the
read. The data stays in this register until the next WRITE
cycle occurs. On the first WRITE cycle after the READ(s),
the stored data from the earlier WRITE will be written
into the SRAM array. This is called a posted write.
A read can be made immediately to an address even if
that address was written in the previous cycle. During
this READ cycle, the SRAM array is bypassed, and data is
FUNCTIONAL BLOCK DIAGRAM
512K x 36
n
SA
LD#
n
E
ADDRESS
REGISTER
COMPARE
(NOTE 2)
n
SA0
CLK
D0
n-1
Q0 SA0’
n
READ
BURST
LOGIC
(NOTE 1)
WRITE#
n
WRITE#
SA0''
C
SA’
C#
OUTPUT
CONTROL
LOGIC
SA0'''
K
36
WRITE
E ADDRESS
REGISTER
INPUT
REGISTER
E
36
36
INPUT
REGISTER
E
n
SA0’
SA0#’
SA0’
36
CLK
WRITE
REGISTER
36
WRITE
DRIVER
36
36
SA0#’
SA0’
n-2
2
x 72
MEMORY
ARRAY
36
SENSE
AMPS
36
36
C
36
OUTPUT
REGISTER
36
0
ZQ
2:1
MUX 36
36
1
36
36
36
36
OUTPUT
BUFFER
E
36
DQ
K#
0
1
36
SA0'''
36
OE
REGISTER
C
R/W#
R/W#
E REGISTER
WRITE#
NOTE:
1. SA0 is toggled at each K and K# rising edge.
2. The compare width is a n-1 bits. The compare is performed only if a WRITE is pending and a READ cycle is requested. If
the address matches, data is routed directly to the device outputs, bypassing the memory array.
3. The functional block diagram illustrates simplified device operation. See truth table, pin descriptions, and timing
diagrams for detailed information. The x8 and x18 operation is the same, with appropriate adjustments of depth and
width.
4. n = 19
18Mb 1.8V V
DD
, HSTL, DDRIIb2 SRAM
MT57W1MH18B_3.p65 – Rev. 3, Pub. 12/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDRIIb2 SRAM
DDR OPERATION (continued)
read instead from the data register storing the recently
written data. This is transparent to the user. This feature
facilitates system data coherency.
The DDR SRAM differs in some ways from its prede-
cessor, the Claymore DDR SRAM. Single data rate opera-
tion is not supported, hence no SD/DD# pin is provided.
Only bursts of two are supported. The need for echo
clocks is reduced or eliminated by the two single-ended
input clocks (C, C#), although tightly controlled echo
clocks (CQ, CQ#) are provided. The SRAM synchronizes
its output data to these data clock rising edges, if pro-
vided. No differential clocks are used in this device. This
clocking scheme provides greater system tuning capabil-
ity than Claymore SRAMs and reduces the number of
input clocks required by the bus master.
between the ZQ pin and V
SS
. The value of the resistor
must be five times the desired impedance. For example,
a 350W resistor is required for an output impedance of
70W. To ensure that output impedance is one fifth the
value of RQ (within 10 percent), the range of RQ is 175W
to 350W. Alternately, the ZQ pin can be connected di-
rectly to V
DD
, which will place the device in a minimum
impedance mode.
Output impedance updates may be required because,
over time, variations may occur in supply voltage and
temperature. The device samples the value of RQ. An
update of the impedance is transparent to the system.
Impedance updates do not affect device operation, and
all data sheet timing and current specifications are met
during an update.
The device will power up with an output impedance
set at 50W. To guarantee optimum output driver imped-
ance after power-up, the SRAM needs 1,024 cycles to
update the impedance. The user can operate the part
with fewer than 1,024 clock cycles, but optimal output
impedance is not guaranteed.
PARTIAL WRITE OPERATIONS
BYTE WRITE operations are supported except for x8
devices, in which nybble write is supported. The active
LOW write controls, BWx# (NWx#), are registered coinci-
dent with their corresponding data. This feature can elimi-
nate the need for some READ-MODIFY-WRITE cycles,
collapsing it to a single BYTE/NYBBLE WRITE operation
in some instances.
CLOCK CONSIDERATIONS
This device utilizes internal delay-locked loops for
maximum output data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry auto-
matically resets the DLL when the absence of input clock
is detected. See Micron Technical Note TN-54-02 for
more information on clock DLL start-up procedures.
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
The DDR SRAM is equipped with programmable im-
pedance output buffers. This allows a user to match the
driver impedance to the system. To adjust the imped-
ance, an external precision resistor (RQ) is connected
APPLICATION EXAMPLE
R = 250Ω
ZQ
SRAM
DQ0:35
SA
LD# R/W# C C# K K#
ZQ
SRAM
DQ0:35
SA
LD# R/W# C C# K K#
R = 250Ω
BUS
MASTER
(CPU
or
ASIC)
DQ
Address
Cycle Start#
R/W#
Source K
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
/2
Vt
R
Vt
NOTE:
In this approach, the second clock pair drives the C and C# clocks, but is delayed such that return data meets data setup
and hold times at the bus master.
18Mb 1.8V V
DD
, HSTL, DDRIIb2 SRAM
MT57W1MH18B_3.p65 – Rev. 3, Pub. 12/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDRIIb2 SRAM
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock pair
by tying C and C# HIGH. In this mode the SRAM will use
K and K# in place of C and C#. This mode provides the
most rapid data output but does not compensate for
system clock skew and flight times.
DEPTH EXPANSION
Depth expansion requires replicating the LD# control
signal for each bank. All other control signals can be
common between banks as appropriate.
2 MEG x 8 PIN ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ4
NC
DQ5
V
DD
Q
NC
NC
NC
NC
NC
DQ7
SA
4
R/W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
NW1#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC
NW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
*Expansion addresses: 10A for 36Mb, 2A for 72Mb
NOTE:
NW0# controls writes to DQ0:DQ3. NW1# controls writes to DQ4:DQ7
Note that 6C is not SA0. The x8 does not permit random start address on the least significant address bit.; SA0 = 0 at the
start of each access.
18Mb 1.8V V
DD
, HSTL, DDRIIb2 SRAM
MT57W1MH18B_3.p65 – Rev. 3, Pub. 12/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDRIIb2 SRAM
1 MEG x 18 PIN ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DD
Q
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
BW1#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC
BW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
*Expansion addresses: (3A was for 18Mb), 10A for 36Mb, 2A for 72Mb
NOTE:
BW0# controls writes to DQ0:DQ8. BW1# controls writes to DQ9:DQ17
18Mb 1.8V V
DD
, HSTL, DDRIIb2 SRAM
MT57W1MH18B_3.p65 – Rev. 3, Pub. 12/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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