CAT1026, CAT1027
Dual Voltage Supervisory
Circuits with I
2
C Serial
2k-bit CMOS EEPROM
http://onsemi.com
The CAT1026 and CAT1027 are complete memory and supervisory
solutions for microcontroller−based systems. A 2k−bit serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together in low power CMOS technology.
Memory interface is via a 400 kHz I
2
C bus.
The CAT1026 and CAT1027 provide a precision V
CC
sense circuit
with five reset threshold voltage options that support 5 V, 3.3 V and
PDIP−8
TSSOP−8
CASE 646AA
CASE 948S
3 V systems. The power supply monitor and reset circuit protects
memory and systems controllers during power up/down and against
brownout conditions. If power supply voltages are out of tolerance
reset signals become active preventing the system microcontroller,
ASIC, or peripherals from operating.
The CAT1026 features two open drain reset outputs: one (RESET)
SOIC−8
drives high and the other (RESET) drives low whenever V
CC
falls
CASE 751BD
below the threshold. Reset outputs become inactive typically 200 ms
after the supply voltage exceeds the reset threshold value. With both
active high and low reset signals, interface to microcontrollers and
other ICs is simple. CAT1027 has only a RESET output. In addition,
the RESET pin can be used as an input for push−button manual reset
MSOP−8
TDFN−8
capability.
CASE 846AD
CASE 511AL
The CAT1026 and CAT1027 provide an auxiliary voltage sensor
input, V
SENSE
, which is used to monitor a second system supply. The
auxiliary high impedance comparator drives the open drain output,
ORDERING INFORMATION
V
LOW
, whenever the sense voltage is below 1.25 V threshold.
For Ordering Information details, see page 13.
The CAT1027 is designed with a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a hardware glitch
halts or “hangs” the system. The CAT1027 features a watchdog timer
interrupt input, WDI.
The on−chip 2k−bit EEPROM memory features a 16−byte page. In addition, hardware data protection is provided by a V
CC
sense circuit that prevents writes to memory whenever V
CC
falls below the reset threshold or until V
CC
reaches the reset
threshold during power up.
Available packages include an 8−pin DIP and surface mount, 8−pin SO, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP
packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint is 3 x 3 mm.
Features
♦
Description
•
Precision V
CC
Power Supply Voltage Monitor
•
•
•
•
•
•
5 V, 3.3 V and 3 V Systems
♦
Five Threshold Voltage Options
Additional Voltage Monitoring
♦
Externally Adjustable Down to 1.25 V
Watchdog Timer (CAT1027 Only)
Active High or Low Reset
♦
Valid Reset Guaranteed at V
CC
= 1 V
400 kHz I
2
C Bus
2.7 V to 5.5 V Operation
Low Power CMOS Technology
•
•
•
•
•
•
•
16−Byte Page Write Buffer
Built−in Inadvertent Write Protection
1,000,000 Program/Erase Cycles
Manual Reset Capability
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−Pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm
foot−print) Packages
♦
TDFN max Height is 0.8 mm
•
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 18
1
Publication Order Number:
CAT1026/D
CAT1026, CAT1027
Table 1. RESET THRESHOLD OPTION
Part Dash
Number
−45
−42
−30
−28
−25
Minimum
Threshold
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORDADDRESS
BU F F E R S
COLUMN
DECODERS
SENSEAMPS
SHIFT REGISTERS
SDA
STA RT/ STOP
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
V CC Monitor
V CC
HIGHVOLTAGE/
TIMING CONTROL
STATE COUNTERS
RESET
SLAVE
ADDRESS
COMPARATORS
SC L
+
-
V REF
Controller
WDI
(CAT1027)
AuxiliaryVoltage Monitor
V SENSE
V REF
+
-
V LOW
RESET RESET
(CAT1026)
http://onsemi.com
2
CAT1026, CAT1027
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
V
LOW
RESET
V
SENSE
V
SS
V
LOW
RESET
V
SENSE
V
SS
1
2
3
4
1
2
3
4
CAT1027
CAT1026
8
7
6
5
8
7
6
5
V
CC
RESET
SCL
SDA
V
CC
WDI
SCL
SDA
(Bottom View)
TDFN Package: 3 mm x 3 mm
0.8 mm maximum height
−
(ZD4)
V
CC
RESET
SCL
SDA
V
CC
WDI
SCL
SDA
8
7
6
5
8
7
6
5
CAT1027
CAT1026
1
2
3
4
1
2
3
4
V
LOW
RESET
V
SENSE
V
SS
V
LOW
RESET
V
SENSE
V
SS
PIN DESCRIPTION
RESET/RESET:
RESET OUTPUTs
(RESET CAT1026 Only)
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
V
SENSE
: AUXILIARY VOLTAGE MONITOR INPUT
The V
SENSE
input is a second voltage monitor which is
compared against CAT1026 and CAT1027 internal
reference voltage of 1.25 V typically. Whenever the input
voltage is lower than 1.25 V, the open drain V
LOW
output
will be driven low. An external resistor divider is used to set
the voltage level to be sensed. Connect V
SENSE
to V
CC
if
unused.
V
LOW
: AUXILIARY VOLTAGE MONITOR OUTPUT
This open drain output goes low when V
SENSE
is less than
1.25 V and goes high when V
SENSE
exceeds the reference
voltage.
WDI
(CAT1027 Only): WATCHDOG TIMER
INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET outputs
will be driven active.
Table 2. PIN FUNCTION
Pin Name
RESET
V
SS
SDA
SCL
RESET
V
CC
V
SENSE
V
LOW
WDI
Function
Active Low Reset Input/Output
Ground
Serial Data/Address
Clock Input
Active High Reset Output
(CAT1026 Only)
Power Supply
Auxiliary Voltage Monitor Input
Auxiliary Voltage Monitor Output
Watchdog Timer Interrupt
(CAT1027 Only)
Table 3. OPERATING TEMPERATURE RANGE
Industrial
Extended
−40°C
to 85°C
−40°C
to 125°C
http://onsemi.com
3
CAT1026, CAT1027
Table 4. CAT102X FAMILY OVERVIEW
Device
Manual Reset
Input Pin
n
n
n
n
n
n
n
n
WDI
n
n
n
Watchdog
Watchdog
Monitor Pin
SDA
SDA
WDI
n
Write
Protection
Pin
n
Independent
Auxiliary Voltage
Sense
RESET:
Active High
and LOW
n
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
n
n
n
2k
2k
2k
2k
2k
2k
2k
NOTE: For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.
SPECIFICATIONS
Table 5. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 s)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
−2.0
to V
CC
+ 2.0
−2.0
to 7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB
V
IL
(Note 3)
V
IH
(Note 3)
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
Test Conditions
V
IN
= GND to V
CC
V
IN
= GND to V
CC
f
SCL
= 400 kHz
V
CC
= 5.5 V
f
SCL
= 400 kHz
V
CC
= 5.5 V
V
CC
= 5.5 V
V
IN
= GND or V
CC
CAT1026
CAT1027
−0.5
0.7 x V
CC
I
OL
= 3 mA
V
CC
= 2.7 V
I
OH
=
−0.4
mA
V
CC
= 2.7 V
V
CC
−
0.75
Min
−2
−10
Typ
Max
10
10
3
1
50
60
0.3 x V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
(SDA, RESET)
Output High Voltage
(RESET)
http://onsemi.com
4
CAT1026, CAT1027
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
V
TH
Parameter
Reset Threshold
Test Conditions
CAT102x−45 (V
CC
= 5.0 V)
CAT102x−42 (V
CC
= 5.0 V)
CAT102x−30 (V
CC
= 3.3 V)
CAT102x−28 (V
CC
= 3.3 V)
CAT102x−25 (V
CC
= 3.0 V)
V
RVALID
V
RT
(Note 4)
V
REF
Reset Output Valid V
CC
Voltage
Reset Threshold Hysteresis
Auxiliary Voltage Monitor
Threshold
Min
4.50
4.25
3.00
2.85
2.55
1.00
15
1.2
1.25
1.3
Typ
Max
4.75
4.50
3.15
3.00
2.70
V
mV
VS
Units
V
3. V
IL
min and V
IH
max are reference values only and are not tested.
4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Table 7. CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
OUT
(Note 5)
C
IN
(Note 5)
Output Capacitance
Input Capacitance
Test
Test Conditions
V
OUT
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
Table 8. AC CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(Note 6)
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R
(Note 5)
t
F
(Note 5)
t
HD; STA
t
SU; STA
t
HD; DAT
t
SU; DAT
t
SU; STO
t
AA
t
DH
t
BUF
(Note 5)
t
WC
(Note 7)
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
50
1.3
5
0.6
0.6
0
100
0.6
900
1.3
0.6
300
300
Parameter
Min
Max
400
100
Units
kHz
ns
ms
ms
ns
ns
ms
ms
ns
ns
ms
ns
ns
ms
ms
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. Test Conditions according to “AC Test Conditions” table.
7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
http://onsemi.com
5
ADI 工业技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
