Preliminary Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
RS8973
Single-Chip SDSL/HDSL Transceiver
The RS8973 is a full-duplex 2B1Q transceiver based on Conexant’s HDSL technology,
with a built-in frequency synthesizer to support variable rate SDSL applications. It offers
2320 kbps operation, low power consumption, and pin-for-pin compatibility with
Bt8970 and Bt8960.
The RS8973 is a highly integrated device that includes all of the active circuitry
needed for a complete 2B1Q transceiver. In the receive portion of the device, a variable
gain amplifier optimizes the signal level according to the dynamic range of the
analog-to-digital converter. Once the signal is digitized, sophisticated adaptive echo
cancellation, equalization, and detection DSP algorithms reproduce the originally
transmitted far-end signal.
In the transmitter, the transmit source and scrambler operation are programmable
through the microcomputer interface. A highly linear digital-to-analog converter with
programmable gain sets the transmission power for optimal performance. A pulse
shaping filter and a low-distortion line driver generate the signal characteristics needed
to drive a large range of subscriber lines at low distortion.
The integrated frequency synthesizer is ideal for variable rate SDSL applications. The
RS8973 can be programmed to operate at data rates ranging from 144 kbps to
2320 kbps, using a single crystal as a reference clock source.
The RS8973 is fully compliant with standards for HDSL 2B1Q transmission. Key to
variable rate applications, it can meet the PSD, output power, and pulse shape
requirements, as specified in ETSI TS 101 135 (formerly ETR 152
)
with the same
support circuit. Therefore, a single design using the RS8973 can be configured through
a simple software command to operate at either 784, 1168, or 2320 kbps and will still
meet these ETSI requirements. No hardware changes are required.
Startup and performance monitoring operations are controlled through the
microprocessor interface. C-language source code supporting these operations is
supplied under a no-fee license agreement from Conexant. The RS8973 includes a
glueless interface to both Intel and Motorola microprocessors.
Distinguishing Features
•
•
•
Supports data rates ranging from
144 kbps to 2320 kbps
Integrated frequency synthesizer
Meets ETSI TS 101 135 (formerly
ETR 152) pulse template, output
power and PSD specifications at 784,
1168 and 2320 kbps data rates,
using the same external support
circuit
Meets ANSI T1/E1.4/94-006 pulse
template, output power and PSD
specifications at 784 kbps.
Pin-for-pin and software compatible
with Bt8970 and Bt8960
Supports automatic rate adaptation
Single-chip 2B1Q transceiver
solution
Low power consumption (under
685 mW at 784 kbps operation)
Glueless interface to Motorola and
Intel processors
Flexible monitoring and control
Backwards compatible with Bt8952,
Bt8960, and Bt8970 software API
commands
ZipStartup™ available for faster link
establishment
RS8953B companion SDSL/HDSL
framers available
JTAG/IEEE Std 1149.1 compliant
100-pin PQFP package
–40
°C
to +85
°C
operation
•
•
•
•
•
•
•
•
•
•
•
•
•
Functional Block Diagram
Applications
Analog
Receive
Variable
Gain
Amplifier
Analog-
to-Digital
Converter
Digital
Signal
Processor
Recovered
Data and
Clock
Framer/
Channel
Unit
Interface
Clock
Synthesizer
MPU
Bus
Analog
Transmit
Microcomputer
Interface
Line
Driver
Pulse
Shaping
Filter
Program-
mable
Gain
DAC
•
•
•
•
•
•
•
•
•
Variable rate data access systems
Data access concentrators
E1 and T1 HDSL transport
Internet connectivity
Voice and/or data Pair Gain systems
N × 64 data transport
ISDN BRI concentrators
Cellular base station data links
Campus modems
Data Sheet
Preliminary Information
8973_001
Transmit
Data
N8973DSD
June 15, 1999
Ordering Information
Model Number
RS8973EPF
Package
100-Pin Plastic Quad Flat Pack
Operating Temperature
–40 °C to +85 °C
Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is
assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant
products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without
notice.
Conexant and “What’s Next in Communications Technologies” are trademarks of Conexant Systems, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
© 1999 Conexant Systems, Inc.
Printed in U.S.A.
All Rights Reserved
Reader Response:
To improve the quality of our publications, we welcome your feedback. Please send comments or
suggestions via e-mail to
Conexant Reader Response@conexant.com.
Sorry, we can't answer your technical
questions at this address. Please contact your local Conexant
sales office
or local field applications engineer if you
have technical questions.
N8973DSD
Conexant
Preliminary Information
Table of Contents
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1.0
System Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
Functional Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.2
1.3
Transmit Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Receive Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Timing Recovery and Clock Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Microcomputer Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Test and Diagnostic Interface (JTAG)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Regenerator Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
2.0
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Transmit Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.2
2.2.1
2.2.2
2.2.3
Symbol Source Selector/Scrambler
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Variable Gain Digital-to-Analog Converter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Pulse-Shaping Filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Analog CT Reconstruction Filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Line Driver
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Variable Gain Amplifier
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Analog-to-Digital Converter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Digital Signal Processor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.3.1
Digital Front-End
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.3.2
Offset Adjustment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3.3
DC Level Meter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3.4
Signal Level Meter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3.5
Overflow Detection and Monitoring
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3.6
Far-End Level Meter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3.7
Far-End Level Alarm
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Impulse Shortening Filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Receive Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.4
N8973DSD
Conexant
Preliminary Information
iii
Table of Contents
RS8973
Single-Chip SDSL/HDSL Transceiver
2.2.5
2.2.6
2.2.7
Echo Canceller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.5.1
Linear Echo Canceller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.5.2
Nonlinear Echo Canceller (NEC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Equalizer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.6.1
Digital Automatic Gain Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.6.2
Feed Forward Equalizer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.6.3
Error Predictor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.6.4
Decision Feedback Equalizer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.6.5
Microcoding
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Detector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.7.1
Slicer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.7.2
Peak Detector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.7.3
Error Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.7.4
Scrambler Module
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.7.5
Sync Detector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.7.6
Detector Meters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Timing Recovery Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Crystal Amplifier
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Clock Synthesizer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3
Timing Recovery and Clock Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.1
2.3.2
2.3.3
2.4
2.5
Channel Unit Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Microcomputer Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.5.1
2.5.2
Source Code
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Microcomputer Read/Write
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.5.2.1
RAM Access Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.5.2.2
Multiplexed Address/Data Bus
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.5.2.3
Separated Address/Data Bus
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Interrupt Request
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Timers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Scratch Pad Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
Test and Diagnostic Interface (JTAG)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
iv
Conexant
Preliminary Information
N8973DSD
RS8973
Single-Chip SDSL/HDSL Transceiver
Table of Contents
3.0
Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
Conventions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.0
Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
3.3
Register Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Register Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
0x00—Global Modes and Status Register (global_modes)
. . . . . . . . . . . . . . . . . . . . . . . . 3-7
0x01—Serial Monitor Source Select Register (serial_monitor_source)
. . . . . . . . . . . . . . . 3-8
0x02—Interrupt Mask Register Low (mask_low_reg)
. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
0x03—Interrupt Mask Register High (mask_high_reg)
. . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
0x04—Timer Source Register (timer_source)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
0x05—IRQ Source Register (irq_source)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
0x06—Channel Unit Interface Modes Register (cu_interface_modes)
. . . . . . . . . . . . . . 3-11
0x07—Receive Phase Select Register (receive_phase_select)
. . . . . . . . . . . . . . . . . . . . 3-12
0x08—Linear Echo Canceller Modes Register (linear_ec_modes)
. . . . . . . . . . . . . . . . . 3-12
0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes)
. . . . . . . . . . . . 3-13
0x0A—Decision Feedback Equalizer Modes Register (dfe_modes)
. . . . . . . . . . . . . . . . . 3-13
0x0B—Transmitter Modes Register (transmitter_modes)
. . . . . . . . . . . . . . . . . . . . . . . 3-14
0x0C—Timer Restart Register (timer_restart)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
0x0D—Timer Enable Register (timer_enable)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
0x0E—Timer Continuous Mode Register (timer_continuous)
. . . . . . . . . . . . . . . . . . . . . 3-16
0x0F—Miscellaneous/Test Register (misc_test)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
0x10, 0x11—Startup Timer 1 Interval Register (sut1_low, sut1_high)
. . . . . . . . . . . . . . 3-16
0x12, 0x13—Startup Timer 2 Interval Register (sut2_low, sut2_high)
. . . . . . . . . . . . . . 3-16
0x14, 0x15—Startup Timer 3 Interval Register (sut3_low, sut3_high)
. . . . . . . . . . . . . . 3-17
0x16, 0x17—Startup Timer 4 Interval Register (sut4_low, sut4_high)
. . . . . . . . . . . . . . 3-17
0x18, 0x19—Meter Timer Interval Register (meter_low, meter_high)
. . . . . . . . . . . . . . . 3-17
0x1A, 0x1B—SNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high)
. . . . 3-17
0x1C, 0x1D—General Purpose Timer 3 Interval Register (t3_low, t3_high)
. . . . . . . . . . 3-17
0x1E, 0x1F—General Purpose Timer 4 Interval Register (t4_low, t4_high)
. . . . . . . . . . . 3-17
0x20—Clock Frequency Select Register (clock_freq_select)
. . . . . . . . . . . . . . . . . . . . . 3-18
0x21—ADC Control Register (adc_control)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
0x22—PLL Modes Register (pll_modes)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
0x23—Test Register (test_reg23)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
0x24, 0x25—Timing Recovery PLL Phase Offset Register
(pll_phase_offset_low, pll_phase_offset_high)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
0x26, 0x27—Receiver DC Offset Register (dc_offset_low, dc_offset_high)
. . . . . . . . . . 3-20
0x28—Transmitter Calibration Register (tx_calibrate)
. . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
0x29—Transmitter Gain Register (tx_gain)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
0x2A, 0x2B—Noise-Level Histogram Threshold Register
(noise_histogram_th_low, noise_histogram_th_high)
. . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
0x2C, 0x2D—Error Predictor Pause Threshold Register
(ep_pause_th_low, ep_pause_th_high)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
0x2E—Scrambler Synchronization Threshold Register (scr_sync_th)
. . . . . . . . . . . . . . 3-22
0x30, 0x31—Far-End High Alarm Threshold Register
(far_end_high_alarm_th_low, far_end_high_alarm_th_high)
. . . . . . . . . . . . . . . . . . . . . 3-22
N8973DSD
Conexant
Preliminary Information
v
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